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SPT5240SIT 参数 Datasheet PDF下载

SPT5240SIT图片预览
型号: SPT5240SIT
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 400 MWPS电流输出数位类比转换器 [10-bit, 400 MWPS Current Output Digital-to-Analog Converter]
分类和应用: 转换器
文件页数/大小: 10 页 / 204 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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SPT5240
DATA SHEET
Pin Configuration
DGND
DV
DD
DV
DD
D3
D4
D5
D6
D7
Pin Assignments
Analog Outputs
IO
P
DAC current output. Full-scale output at 11…11
input code.
Complementary current output. Full-scale output
IO
N
at 00…00 input code.
Digital Inputs
D0 – D9 Digital inputs (D0 = LSB).
PWD
Power down mode pin. Active high. Internally
pulled down.
CLK
Clock input pin. Data is latched on the rising edge.
Reference
I
SET
Full-scale adjust control. Connection for
reference-current setting resistor.
Power
AGND
DGND
AV
DD
DV
DD
N/C
Analog Supply Ground.
Digital Supply Ground.
Analog +3.3V supply.
Digital +3.3V supply.
No Connect
32
31
30
29
28
27
26
D2
D1
DV
DD
D0
DGND
CLK
DGND
AGND
1
2
3
4
5
6
7
8
25
24
23
22
D8
DGND
D9
DGND
PWD
AV
DD
AGND
I
SET
SPT5240SIT
32-pin LQFP
21
20
19
18
17
10
11
12
13
14
15
AV
DD
IO
P
IO
N
AV
DD
AGND
AGND
Theory of Operation
The SPT5240 is a 10-bit 400 MWPS digital-to-analog
converter. It integrates a DAC core with a bandgap reference
and operates from a +3.3V power supply.
The DAC architecture is a compound differential current
output DAC consisting of a 6-bit fully segmented DAC for
the MSBs and a 4-bit fully segmented DAC for the LSBs.
The input cell, followed by a master-slave latch, buffers the
digital inputs. A 6:64 decoder decodes the digital data for
the MSBs, and a 4:16 decoder does so for the LSBs. The
N
CLK
t
S
t
H
AGND
N/C
16
9
outputs of the decoders are latched using a second bank
of master-slave latches whose outputs then drive differential
current switches, which steer the appropriate current to
the IO
P
or IO
N
outputs.
The analog (AV
DD
) and digital (DV
DD
) power supplies are
separated on chip to allow flexibility in the interface board.
The analog (AGND) and digital (DGND) are separated on
chip. Circuit board ground planes should be separated and
tied together with a ferrite bead.
N+1
Digital
Inputs
N
N+1
t
D
N+2
N+3
VO
P
1 LSB
N-2
VO
N
N-1
N
N+1
1 LSB
t
settling
NOTE:
Not to scale. For definition purposes only.
Figure 1: Timing Diagram
REV. 1 June 2003
7