DATA SHEET
SPT5240
Compliance Voltage
The maximum terminal output voltage for which the device
will provide the specified current output characteristics.
Specification Definitions
Differential Linearity Error (DLE) or
Differential Nonlinearity (DNL)
In an ideal DAC, output transitions between two adjacent
codes are 1 LSB apart. Differential Linearity Error is the
deviation, expressed in LSBs, from this ideal value.
Harmonic
1. Of a sinusoidal wave, an integer multiple of the frequency
of the wave. Note: The frequency of the sine wave is called
the fundamental frequency or the first harmonic, the
second harmonic is twice the fundamental frequency, the
third harmonic is three times the fundamental frequency, etc.
Integral Linearity Error (ILE) or
Integral Nonlinearity (INL)
The ideal transfer for a DAC is a straight line drawn between
"zero-scale" output and "full-scale" output. ILE is the
deviation of the output from the straight line. The deviation
of the output at each code is measured and compared to the
ideal output at that code. ILE may also be expressed as a
sum of DLE starting from code 0…0 to the code that ILE
measurement is desired.
2. Of a periodic signal or other periodic phenomenon, such
as an electromagnetic wave or a sound wave, a component
frequency of the signal that is an integer multiple of the
fundamental frequency. Note: The fundamental frequency
is the reciprocal of the period of the periodic phenomenon.
Total Harmonic Distortion (THD)
The ratio of the sum of the power of first 9 harmonics above
the fundamental frequency to the power of the fundamental
frequency. Usually expressed in dBc.
Monotonic
A digital-to-analog converter is considered monotonic if
the analog output never decreases as the code value at the
input increases. A DLE less than -1 LSB would indicate a
non-monotonic DAC.
Spurious Free Dynamic Range (SFDR)
The ratio of the fundamental sinusoidal power to the power
of the single largest harmonic or spurious signal within the
range of the 9th harmonic.
Offset Error
The deviation, from ideal, at the DAC output when set to
zero-scale. In the current output DAC there should be no
current flow at zero-scale. Therefore, Offset Error is the
amount of current measured with the DAC set to zero-scale.
Clock Feedthrough
The ratio of the full-scale output to the peak-to-peak noise
generated at the DAC output by input clock transitions.
Expressed in dBFS.
Full-Scale Error
The ideal maximum full-scale current output of the DAC is
determined by the value of R . Full-scale error is the
deviation of the output from ideal with the offset error
included.
Major Code Transition
SET
The DAC code transition between 011…1 and 100…0 is
referred to as major code transition. This transition often
involves maximum number of internal circuit elements to
switch states, resulting in worst DLE, ILE, glitch, etc.
Gain Error
The ideal maximum full-scale current output of the DAC is
Glitch Energy
determined by the value of R . Gain error is the deviation
SET
A glitch is a switching transient that appears in the output of
a DAC during a code transition. Glitch energy is measured as
a product of the output voltage and time duration for major
code transition, expressed in pV-s.
of the output from ideal with the offset error removed.
Full-Scale Output
The maximum current output available for a given value of
R
. In the SPT5240 IOP is full-scale at code 1111111111
Output Rise Time
The amount of time for the output to change from 10%
to 90% of the full-scale voltage, for a positive full scale
transition from zero-scale to full-scale.
SET
and IO is full-scale at code 0000000000.
N
Zero-Scale Output
The minimum current output, ideally zero amps. In the
SPT5240 IO is zero-scale at code 0000000000 and IO
Output Fall Time
P
N
The amount of time for the output to change from 90%
to 10% of the full-scale voltage, for a negative full scale
transition from full-scale to zero-scale.
is zero-scale at code 1111111111.
6
REV. 1 June 2003
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
