Data Sheet
For applications where jitter may limit the obtainable per-
formance, it is of utmost importance to limit the clock
jitter. This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specifications) and make sure the clock distribution is well
controlled. It might be advantageous to use analog power
and ground planes to ensure low noise on the supplies
to all circuitry in the clock distribution. It is of utmost im-
portance to avoid crosstalk between the ADC output bits
and the clock and between the analog input signal and
the clock since such crosstalk often results in harmonic
distortion.
Clock Input and Jitter Considerations
Typicallyhigh-speedADCsusebothclockedgestogenerate
internal timing signals. In the CDK8307 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% is acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine wave
can be connected directly to the input pins. For CMOS
inputs, the CLKN pin should be connected to ground, and
the CMOS clock signal should be connected to CLKP. For
differential sine wave clock input the amplitude must be
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter per-
formance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
at least ±0.8V .
pp
The quality of the input clock is extremely important for
high-speed, high-resolution ADCs. The contribution to
SNR from clock jitter with a full scale signal at a given
frequency is shown in equation below.
If the clock is generated by other circuitry, it should be re-
timed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
•
•
•
•
SNR
= 20 log (2 π F εt)
jitter
IN
where F is the signal frequency, and εt is the total rms
IN
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
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www.cadeka.com
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