PRELIMINARY
Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
DC Accuracy
Parameter
No Missing Codes
Offset Error
Gain Error
Gain Matching
Conditions
Min
Typ
Guaranteed
Max
Units
CDK8307
12/13-bit,
20/40/50/65MSPS,
Eight Channel, Ultra Low Power ADC with LVDS
Offset error after digital offset cancellation
-6
Gain matching between channels. ±3sigma
value at worst case conditions.
12-bit level
12-bit level
-0.5
1
6
0.5
±0.2
±0.6
V
AVDD
/2
LSB
%FS
%FS
LSB
LSB
V
V
CM
+0.2
V
V
pp
pF
MHz
DNL
INL
V
CMO
Differential Non-Linearity
Integral Non-Linearity
Common Mode Voltage Output
Input Common Mode
Full Scale Range
Input Capacitance
Bandwidth
Analog Input
V
CMI
V
FSR
Analog input common mode voltage
Differential input voltage range
Differential input capacitance
Input bandwidth
500
1.7
Digital and output driver supply voltage
1.7
1.7
1.8
1.8
1.8
2.0
2.0
3.6
V
CM
-0.1
2.0
2
Power Supply
AVDD
DVDD
OVDD
Analog Supply Voltage
Digital Supply Voltage
Digital CMOS Input Supply Voltage
V
V
V
Electrical Characteristics - CDK8307A
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Performance
SNR
SINAD
SFDR
HD2
HD3
ENOB
Crosstalk
Parameter
Signal to Noise Ratio
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
Conditions
F
IN
= 8MHz
F
IN
= 8MHz
F
IN
= 8MHz
F
IN
= 8MHz
F
IN
= 8MHz
Signal applied to 7 channels (F
IN0
).
Measurement taken on one channel with full
scale at F
IN1
. F
IN1
= 8MHz, F
IN0
= 9.9MHz
Min
Typ
72.2
71.5
82
95
82
11.6
95
Max
Units
dBFS
dBFS
dBc
dBc
dBc
bits
dBc
Power Supply
Analog supply current
Digital supply current
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
Power dissipation with all chs in sleep mode
Power dissipation savings per channel off
20
15
Digital and output driver supply
47
50
85
90
175
10
43
44
16
mA
mA
mW
mW
mW
μW
mW
mW
mW
MSPS
MSPS
Rev 0.4.0
Clock Inputs
Maximum Conversion Rate
Minimum Conversion Rate
©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
