PRELIMINARY
Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted)
Symbol
Clock Inputs
Duty Cycle
Compliance
Input range
Input range
Input common mode voltage
Input capacitance
Differential input swing
Differential input swing, sine wave clock input
Keep voltages within gnd and voltage of AVDD
Differential
V
OVDD
≥ 3.0V
V
OVDD
= 1.7V – 3.0V
V
OVDD
≥ 3.0V
V
OVDD
= 1.7V – 3.0V
2
0.8
•
V
OVDD
0
0
-10
-10
3
LVDS
247
1.125
Default/Optional
454
1.375
mV
V
0.8
0.2
•
V
OVDD
10
10
20
200
800
0.3
2
80
200
800
V
AVDD
-0.3
%high
mV
pp
mV
pp
V
pF
V
V
V
V
μA
μA
pF
Parameter
Conditions
Min
Typ
Max
Units
CDK8307
12/13-bit,
20/40/50/65MSPS,
Eight Channel, Ultra Low Power ADC with LVDS
CMOS, LVDS, LVPECL
Logic Inputs (CMOS)
V
IH
V
IL
I
IH
I
IL
C
I
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
Compliance
V
OUT
V
CM
Digital Output Voltage
Output Common Mode Voltage
Output Coding
Data Outputs (LVDS)
Offset Binary/2‘s Complement
0.8
<0.5
ns
ps
900
0.5
1
14
clock
cycles
μs
clk cycles
clk cycles
ps
ns
55
2.5
% LCLK
cycle
% LCLK
cycle
ns
ns
Timing Characteristics
T
AP
Aperture Delay
Aperture Jitter
Power Down
Sleep Mode
Out Of Range Recovery Time
Pipeline Delay
LCLK to Data Delay Time
Clock Propagation Delay
LVDS Bit-Clock Duty-Cycle
Frame clock cycle-to-cycle jitter
T
EDGE
T
CLKEDGE
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
ε
RMS
T
PD
T
SLP
T
OVR
T
LAT
t
data
T
PROP
Start up time from Power Down to Active
Mode. References have reached 99% of final
value. (See section Clock Frequency)
Start up time from Sleep Mode to Active Mode
350
LVDS Output Timing Characterisctics
Excluding programmable phase shift
50
TBD
45
Data Rise- and Fall Time
Clock Rise- and Fall Time
Calculated from -100mV to +100mV,
and vice-versa
Calculated from -100mV to +100mV,
and vice-versa
TBD
TBD
Rev 0.4.0
©2009 CADEKA Microcircuits LLC
www.cadeka.com
13
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
