PRELIMINARY
Data Sheet
Pin Assignments
(Continued)
Pin No.
16
19
20
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
45
62, 64, 66, 67, 69
65
71
72
75
76
77
78
Pin Name
PD
LCKP
LCKN
D1P
D1N
D2P
D2N
D3P
D3N
D4P
D4N
D5P
D5N
D6P
D6N
D7P
D7N
D8P
D8N
FCLKP
FCLKN
RESETN
NC
VCM
CLKP
CLKN
OVDD
CSN
SDATA
SCLK
Description
Power-down input
LVDS bit clock, positive output
LVDS bit clock, negative output
LVDS channel 1, positive output
LVDS channel 1, negative output
LVDS channel 2, positive output
LVDS channel 2, negative output
LVDS channel 3, positive output
LVDS channel 3, negative output
LVDS channel 4, positive output
LVDS channel 4, negative output
LVDS channel 5, positive output
LVDS channel 5, negative output
LVDS channel 6, positive output
LVDS channel 6, negative output
LVDS channel 7, positive output
LVDS channel 7, negative output
LVDS channel 8, positive output
LVDS channel 8, negative output
LVDS frame clock (1x), positive output
LVDS frame clock (1x), negative output
Reset SPI interface
Not connected
Common mode output pin, 0.5 AVDD
Positive differential input clock
Negative differential input clock.
Digital CMOS inputs supply voltage (1.7V to 3.6V)
Chip select enable. Active low.
Serial data input
Serial clock input
CDK8307
12/13-bit,
20/40/50/65MSPS,
Eight Channel, Ultra Low Power ADC with LVDS
Rev 0.4.0
©2009 CADEKA Microcircuits LLC
www.cadeka.com
8
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
