Data Sheet
Electrical Characteristics - CDK2307A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
72.5
72.2
72.1
71.6
72.4
72
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
71.5
SNR
Signal to Noise Ratio
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
71
75
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
71.7
71.3
87
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
85
dBc
80
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
80
dBc
-90
-95
-95
-95
-87
-85
-80
-80
11.7
11.7
11.6
11.6
dBc
-85
dBc
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
-75
dBc
HD3
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
11.5
bits
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
bits
FIN = 20MHz
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-105
dB
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
11.6
1.8
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
2.9
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
2.4
mA
Analog Power Dissipation
Digital Power Dissipation
20.9
9.2
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
30.1
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.9
20.5
9.2
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
20
MSPS
MSPS
15
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www.cadeka.com
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