Data Sheet
Pin Assignments (Continued)
Pin No.
19
Pin Name
Description
CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high.
20
DFRMT
PD_N
Data format selection. 0: Offset Binary, 1: Two's Complement
21
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up,
always apply Power Down mode before using Active Mode to reset chip.
22
24, 41, 58
25, 40, 57
26
OE_N_1
OVDD
OVSS
D1_0
Output Enable Channel 0. Tristate when high.
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
Output Data Channel 1 (LSB, 13-bit output or 1Vpp full scale range )
Output Data Channel 1 (LSB, 12-bit output 2Vpp full scale range)
Output Data Channel 1
27
D1_1
28
D1_2
29
D1_3
Output Data Channel 1
30
D1_4
Output Data Channel 1
31
D1_5
Output Data Channel 1
32
D1_6
Output Data Channel 1
33
D1_7
Output Data Channel 1
34
D1_8
Output Data Channel 1
35
D1_9
Output Data Channel 1
36
D1_10
D1_11
D1_12
ORNG_1
CLK_EXT
D0_0
Output Data Channel 1
37
Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data Channel 1 (MSB for 2Vpp full scale range)
Out of Range flag Channel 1. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels.
Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range)
Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range)
Output Data Channel 0
38
39
42
43
44
D0_1
45
D0_2
46
D0_3
Output Data Channel 0
47
D0_4
Output Data Channel 0
48
D0_5
Output Data Channel 0
49
D0_6
Output Data Channel 0
50
D0_7
Output Data Channel 0
51
D0_8
Output Data Channel 0
52
D0_9
Output Data Channel 0
53
D0_10
D0_11
D0_12
ORNG_0
OE_N_0
Output Data Channel 0
54
Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data Channel 0 (MSB for 2Vpp full scale range)
Out of Range flag Channel 0. High when input signal is out of range.
Output Enable Channel 0. Tristate when low.
Bias control bits for the buffer driving pin CM_EXT
55
56
59
CM_EXTBC_1,
CM_EXTBC_0
00: Off
10: 500uA
10: 50uA
11: 1mA
60, 61
62, 63
Sleep Mode
00: Sleep Mode
10: Channel 1 active
SLP_N_1,
SLP_N_0
01: Channel 0 active
11: Both channels active
©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
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