Data Sheet
Pin Assignments
(Continued)
Pin No.
19
20
21
22
24, 41, 58
25, 40, 57
26
27
28
29
30
31
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
59
60, 61
Pin Name
CLK_EXT_EN
DFRMT
PD_N
OE_N_1
OVDD
OVSS
D1_0
D1_1
D1_2
D1_3
D1_4
D1_5
D1_6
D1_7
D1_8
D1_9
D1_10
D1_11
D1_12
ORNG_1
CLK_EXT
D0_0
D0_1
D0_2
D0_3
D0_4
D0_5
D0_6
D0_7
D0_8
D0_9
D0_10
D0_11
D0_12
ORNG_0
OE_N_0
CM_EXTBC_1,
CM_EXTBC_0
SLP_N_1,
SLP_N_0
Description
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
CDK2307
Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up,
always apply Power Down mode before using Active Mode to reset chip.
Output Enable Channel 0. Tristate when high.
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
Output Data Channel 1 (LSB, 13-bit output or 1V
pp
full scale range )
Output Data Channel 1 (LSB, 12-bit output 2V
pp
full scale range)
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1 (MSB for 1V
pp
full scale range, see Reference Voltages section)
Output Data Channel 1 (MSB for 2V
pp
full scale range)
Out of Range flag Channel 1. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels.
Output Data Channel 0 (LSB, 13 bit output or 1Vpp full scale range)
Output Data Channel 0 (LSB, 12 bit output 2Vpp full scale range)
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0 (MSB for 1V
pp
full scale range, see Reference Voltages section)
Output Data Channel 0 (MSB for 2V
pp
full scale range)
Out of Range flag Channel 0. High when input signal is out of range.
Output Enable Channel 0. Tristate when low.
Bias control bits for the buffer driving pin CM_EXT
00: Off
10: 50uA
10: 500uA
11: 1mA
Sleep Mode
00: Sleep Mode
10: Channel 1 active
01: Channel 0 active
11: Both channels active
Rev 2A
62, 63
©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
