Data Sheet
Pin Configuration
CM_EXTBC_0
CM_EXTBC_1
QFN-40
SLP_N
OVDD
OVDD
D_12
D_10
D_11
D_9
D_8
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
40
39
38
37
36
35
34
33
32
DVDD
CM_EXT
AVDD
AVDD
IP
IN
AVDD
DVDDCLK
CLKP
CLKN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
D_7
D_6
D_5
CLK_EXT
OVDD
OVDD
ORNG
D_4
D_3
D_2
CDK1307
QFN-40
27
26
25
24
23
22
21
DFRMT
OE_N
OVDD
OVDD
DVDD
DVDD
D_0
Pin Assignments
Pin No.
0
1, 11, 16
2
3, 4, 7
5, 6
8
9
10
12
13
14
15
17, 18, 25,
26, 36, 37
19
20
21
22
Pin Name
VSS
DVDD
CM_EXT
AVDD
IP, IN
DVDDCLK
CLKP
CLKN
CLK_EXT_EN
DFRMT
PD_N
OE_N
OVDD
D_0
D_1
D_2
D_3
Description
Ground connection for all power domains. Exposed pad
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
Analog supply voltage, 1.8V
Analog input (non-inverting, inverting)
Clock circuitry supply voltage, 1.8V
Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up
always apply Power Down mode before using Active Mode to reset chip.
Output Enable. Tristate when high
I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V
Output Data (LSB, 13-bit output or 1V
pp
full scale range)
Output Data (LSB, 12-bit output 2V
pp
full scale range)
Output Data
Output Data
CLK_EXT_EN
PD_N
D_1
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
2
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
