Shibasoku #725
Test Disk
Through
Lch
CD
Player
DEM-
PCM1717
THD
Meter
DAI
PGA
Digital
11th-order
LPF
Rch
0dB/60dB
30KHz LPF on
For test of S/N ratio and Dynamic Range, A-filter ON.
FIGURE 17. Test Block Diagram.
TEST CONDITIONS
Figure 17 illustrates the actual test conditions applied to
PCM1717 in production. The 11th-order filter is necessary
in the production environment for the removal of noise
resulting from the relatively long physical distance between
the unit and the test analyzer. In most actual applications, the
3rd-order filter shown in Figure 16 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –89dB when the external 20kHz 11th-
order filter is used.
110
105
100
95
Multi-level
90
85
80
75
PWM
70
65
60
EVALUATION FIXTURES
0
100
200
300
400
500
600
Three evaluation fixtures are available for PCM1717.
Clock Jitter (ps)
DEM-PCM1717
FIGURE 18. Simulation Results of Clock Jitter Sensitivity.
This evaluation fixture is primarily intended for quick evalu-
ation of the PCM1717’s performance. DEM-PCM1717 can
accept either an external clock or a user-installed crystal
oscillator. All of the functions can be controlled by on-board
switches. DEM-PCM1717 does not contain a receiver chip
or an external low pass filter. DEM-PCM1717 requires a
single +5V power supply.
2
1
14.4ps
0
OUT-OF-BAND NOISE CONSIDERATIONS
Delta-sigma DACs are by nature very sensitive to jitter on
the master clock. Phase noise on the clock will result in an
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons delta-
sigma DACs are prone to jitter sensitivity is the large
quantization noise when the modulator can only achieve two
discrete output levels (0 or 1). The multi-level delta-sigma
DAC has improved theoretical SNR because of multiple
output states. This reduces sensitivity to jitter. Figure 18
contrasts jitter sensitivity between a one-bit PWM type DAC
and multi-level delta-sigma DAC. The data was derived
using a simulator, where clock jitter could be completely
synthesized.
–1
48fs
2
FIGURE 19. Simulation Method for Clock Jitter.
®
14
PCM1717
BB [ BURR-BROWN CORPORATION ]
