POWER SUPPLY
CONNECTIONS
PCM1717 has two power supply connections: digital (VDD
)
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 12. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
and analog (VCC). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condi-
tion, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8-times interpolation filter is 48fS for
a 384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 13.
An application circuit to avoid a latch-up condition is shown
in Figure 11.
Digital
Analog
Power Supply
Power Supply
3rd-ORDER ∆Σ MODULATOR
VDD
VCC
20
DGND
AGND
0
–20
–40
FIGURE 11. Latch-up Prevention Circuit.
–60
–80
BYPASSING POWER SUPPLIES
–100
–120
–140
–160
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 10 for optimal values of bypass
capacitors.
0
5
10
15
20
25
THEORY OF OPERATION
Frequency (kHz)
The delta-sigma section of PCM1717 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format.
FIGURE 13. Quantization Noise Spectrum.
+
–
+
–
+
+
+
+
Z–1
Z–1
Z–1
In
8fS
18-Bit
+
+
+
5-level Quantizer
4
3
2
1
0
Out
48fS (384fS)
64fS (256fS)
FIGURE 12. 5-Level ∆Σ Modulator Block Diagram.
®
12
PCM1717
BB [ BURR-BROWN CORPORATION ]
