1 f/s
Left-channel Data
Right-channel Data
LRCIN (pin 4)
BCKIN (pin 6)
Audio Data Word = 16-Bit
MSB
LSB
MSB
LSB
DIN (pin 5)
14 15 16
1
2
3
14 15 16
1
2
3
3
14 15 16
Audio Data Word = 18-Bit
DIN (pin 5)
MSB
1
LSB
MSB
1
LSB
16 17 18
2
3
16 17 18
2
16 17 18
FIGURE 5. “Normal” Data Input Timing.
1 f/s
Left-channel Data
Right-channel Data
LRCIN (pin 4)
BCKIN (pin 6)
Audio Data Word = 16-Bit
DIN (pin 5)
MSB
1
LSB
MSB
LSB
2
2
3
3
14 15 16
1
2
2
3
3
14 15 16
1
1
2
2
Audio Data Word = 18-Bit
DIN (pin 5)
MSB
1
LSB
16 17 18
MSB
1
LSB
16 17 18
FIGURE 6. “I2S” Data Input Timing.
Bit 3 is used as an attenuation control. When bit 3 is set
HIGH, the attenuation data on Register 0 is used for both
channels, and the data in Register 1 is ignored. When bit 3
is LOW, each channel has separate attenuation data.
50% of VDD
LRCIN
tBCH
tBCL
tLB
Bits 4 through 7 are used to determine the output format, as
shown in Table V:
50% of VDD
50% of VDD
BCKIN
DIN
tBL
tBCY
PL0 PL1 PL2 PL3 Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
MUTE
R
L
(L + R)/2
MUTE
MUTE
tDH tDS
BCKIN Pulsewidth (High Level)
BCKIN Pulsewidth (Low Level)
BCKIN Pulse Cycle Time
BCKIN Rising Edge ➝ LRCIN Edge
LRCIN Edge ➝ BCKIN Rising Edge
DIN Setup Time
tBCH
tBCL
tBCY
tBL
tLB
tDS
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
R
L
(L + R)/2
MUTE
R
REVERSE
STEREO
L
L
L
DIN Hold Time
tDH
L
L
(L + R)/2
MUTE
R
FIGURE 7. Data Input Timing.
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
L
Bit 1 is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is LOW, a HIGH state on LRCIN is used
for the left channel, and a LOW state on LRCIN is used for
the right channel. When bit 1 is HIGH the polarity of LRCIN
is reversed.
(L + R)/2
MONO
TABLE V. PCM1717 Output Mode Control.
REGISTER RESET STATES
After reset, each register is set to a predetermined state:
Bit 2 is used to select the input word length. When bit 2 is
LOW, the input word length is set for 16 bits; when bit 2 is
HIGH, the input word length is set for 18 bits.
Register 0
Register 1
Register 2
Register 3
0000 0000 1111 1111
0000 0010 1111 1111
0000 0100 0000 0000
0000 0110 1001 0000
®
10
PCM1717
BB [ BURR-BROWN CORPORATION ]
