ATTENUATION DATA LOAD CONTROL
Bits 3 (OPE) and 4 (IZD) are used to control the infinite zero
detection features. Tables II through IV illustrate the rela-
tionship between IZD, OPE, and RSTB (reset control):
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation. The attenuation level
is given by:
DATA INPUT
DAC OUTPUT
Zero
Other
Zero
Forced to BPZ(1)
IZD = 1
IZD = 0
Normal
Zero(2)
Other
Normal
ATT = 20log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254
TABLE II. Infinite Zero Detection (IZD) Function.
y = x + 1, when x = 255
SOFTWARE MODE
INPUT
DATA INPUT
DAC OUTPUT
X is the user-determined step number, an integer value
between 0 and 255.
Zero
Other
Zero
Forced to BPZ(1)
Forced to BPZ(1)
Controlled by IZD
Normal
Enabled
Enabled
Enabled
Enabled
OPE = 1
OPE = 0
Example:
let x = 255
Other
255+1
TABLE III. Output Enable (OPE) Function.
ATT = 20 log
ATT = 20 log
ATT = 20 log
ATT = 20 log
= 0dB
= –0.068dB
= –48.16dB
= –∞
256
SOFTWARE
MODE
INPUT
let x = 254
let x = 1
let x = 0
DATA INPUT
DAC OUTPUT
254
Zero
Other
Zero
Controlled by OPE and IZD
Controlled by OPE and IZD
Forced to BPZ(1)
Enabled
Enabled
Disabled
Disabled
256
RSTB = “HIGH”
RSTB = “LOW”
Other
Forced to BPZ(1)
1
256
TABLE IV. Reset (RSTB) Function.
NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to
output amplifier.
0
256
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65,536 cycles of BCKIN,
the output will only be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
REGISTER 1
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
IZD controls the operation of the zero detect feature: when
IZD is “LOW”, the zero detect circuit is off. Under this
condition, no automatic muting will occur if the input is
continuously zero. When IZD is “HIGH”, the zero detect
feature is enabled. If the input data is continuously zero for
65,536 cycle of BCKIN, the output will be immediately
forced to a bipolar zero state (VCC/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero, there
may be an audible click. PCM1717 allows the zero detect
feature to be disabled so the user can implement an external
muting circuit.
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0-7 (AR0-AR7) control the level of
attenuation.
REGISTER 2
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B0
res res res res res A1 A0 res res res res IZD OPE DM1 DM0 MUTE
Register 2 is used to control soft mute, digital de-emphasis,
disable, and infinite zero detect. Bit 0 is used for soft mute;
a HIGH level on bit 0 will cause the output to be muted.
Bits 1 and 2 are used to control digital de-emphasis as
shown below:
REGISTER 3
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1
B0
res res res res res A1 A0 res PL3 PL2 PL1 PL0 ATC IW LRP IIS
BIT 1 (DM0)
BIT 2 (DM1)
DE-EMPHASIS
0
1
0
1
0
0
1
1
De-emphasis disabled
De-emphasis enabled at 48kHz
De-emphasis enabled at 44.1kHz
De-emphasis enabled at 32kHz
Register 3 is used to select the I/O data formats. Bit 0 (IIS)
is used to control the input data format. If the input data
source is normal (16- or 18-bit, MSB first, right-justified),
set bit 0 “LOW”. If the input format is IIS, set bit 0 “HIGH”.
®
9
PCM1717
BB [ BURR-BROWN CORPORATION ]
