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DAC1220E 参数 Datasheet PDF下载

DAC1220E图片预览
型号: DAC1220E
PDF下载: 下载PDF文件 查看货源
内容描述: 20位低功耗数位类比转换器 [20-Bit Low Power DIGITAL-TO-ANALOG CONVERTER]
分类和应用: 转换器数模转换器光电二极管PC
文件页数/大小: 14 页 / 125 K
品牌: BB [ BURR-BROWN CORPORATION ]
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MSB (Bit Order) Bit—The MSB bit controls the order in  
which bits within a byte of data are read or written (either  
most significant bit first or least significant bit first) as  
follows:  
Full-Scale Calibration Register (FCR)  
The FCR is a 24-bit register which contains the full-scale  
correction factor that is applied to the digital input before it  
is transferred to the modulator. The contents of this register  
will be the result of a self-calibration, or written to by the  
user.  
MSB  
0
1
MSB-First  
LSB-First  
Default  
The FCR is both readable and writable via the serial inter-  
face. For applications requiring an accurate system calibra-  
tion, a system calibration can be performed, the results  
averaged, and a more precise value written back to the FCR.  
MD1 - MD0 (Operating Mode) Bits—The Operating Mode  
bits control the calibration functions of the DAC1220. The  
Normal mode is used to perform conversions. The Self-  
Calibration mode is a one-step calibration sequence that  
calibrates both the offset and full scale.  
The actual FCR value after calibration will change from part  
to part and with configuration, temperature, and power  
supply.  
In addition, be aware that the contents of the FCR are not  
used to directly correct the digital input. Rather, the correc-  
tion is a function of the FCR value. This function is linear  
and two known points can be used as a basis for interpolat-  
ing intermediate values for the FCR. The contents of the  
FCR are in unsigned binary format. This is not affected by  
the DF bit in the Command register.  
MD1  
MD0  
0
0
1
1
0
1
0
1
Normal Mode  
Self-Cal  
Sleep  
X
Offset Calibration Register (OCR)  
MSB  
Byte 2  
The OCR is a 24-bit register containing the offset correction  
factor that is used to apply a correction to the digital input  
before it is transferred to the modulator. The results of the  
self-calibration process will be written to this register.  
FCR23 FCR22 FCR21 FCR20 FCR19 FCR18 FCR17 FCR16  
Byte 1  
FCR15 FCR14 FCR13 FCR12 FCR11 FCR10 FCR9  
FCR8  
LSB  
Byte 0  
The OCR is both readable and writable via the serial inter-  
face. For applications requiring a more accurate calibration,  
a calibration can be performed, the results averaged, and a  
more precise offset calibration value written back to the  
OCR.  
FCR7  
FCR6  
FCR5  
FCR4  
FCR3  
FCR2  
FCR1  
FCR0  
TABLE VII. Full-Scale Calibration Register.  
Data Input Register (DIR)  
The actual OCR value after calibration will change from part  
to part and with configuration, temperature, and power supply.  
The DIR is a 24-bit register which contains the digital input  
value (see Table VIII). The register is latched on the falling  
edge of the last bit of the last byte sent. The contents of the  
DIR are then loaded into the modulator. This means that the  
DIR register can be updated after sending 1, 2, or 3 bytes,  
which is determined by the MB1 and MB0 bits in the  
Instruction Register. The contents of the DIR can be Offset  
Two’s Complement or Straight Binary.  
In addition, be aware that the contents of the OCR are not  
used to directly correct the digital input. Rather, the correc-  
tion is a function of the OCR value. This function is linear  
and two known points can be used as a basis for interpolat-  
ing intermediate values for the OCR.  
The results of calibration are averaged, Offset Two's Comple-  
ment adjusted, and placed in the OCR.  
MSB  
Byte 2  
MSB  
Byte 2  
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16  
DIR23  
DIR22 DIR21 DIR20 DIR19 DIR18 DIR17  
DIR16  
Byte 1  
Byte 1  
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR9  
OCR8  
LSB  
DIR15  
DIR7  
DIR14 DIR13 DIR12 DIR11 DIR10  
DIR9  
DIR1  
DIR8  
LSB  
DIR0  
Byte 0  
Byte 0  
OCR7  
OCR6  
OCR5  
OCR4  
OCR3  
OCR2  
OCR1  
OCR0  
DIR6  
DIR5  
DIR4  
DIR3  
DIR2  
TABLE VI. Offset Calibration Register.  
TABLE VIII. Data Input Register.  
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