Command Register (CMR)
The CMR controls all of the functionality of the DAC1220.
The new configuration is latched in on the negative transi-
tion of SCLK for the last bit of the last byte of data being
written to the command register. The organization of the
CMR is comprised of 16 bits of information in 2 bytes of 8
bits each.
MSB
ADPT
CALPIN
SH
Byte 1
0
Byte 0
RES
CLR
DF
DISF
BD
MSB
MD1
1
0
CRST
0
LSB
MD0
RES (Resolution) Bit—The
Resolution bit selects either
16-bit or 20-bit resolution.
RES
0
1
16-Bit
20-Bit
Default
CLR (Clear) Bit—The
CLR bit synchronously resets the
data input register to zero. The analog output will be based
on the DF bit—if 1, the output will be 0V; if 0, the output
will be V
REF
.
CLR
NOTE: In order to obtain optimal performance, the default bit states for
the Command Register should be used (refer to Table VI). The only ex-
ception is the SH bit—the default bit state is 0, however, the bit should be
set to 1 for optimal performance.
0
1
OFF
ON
Default
TABLE V. Command Register.
ADPT (Adaptive Filter Disable) Bit—The
ADPT bit de-
termines if the adaptive filter is enabled or disabled. When
the Adaptive Filter is enabled, the DAC1220 does fast
settling only when there is an output step of larger than
≈
40mV. For small changes in the data, fast settling is not
necessary. When ADPT = 1, the Adaptive Filter is disabled
and the DAC1220 will not look at the size of a step to
determine the necessity of using fast settling. In either case,
fast settling can be defeated if DISF = 1.
ADPT
0
1
Enabled (default)
Disabled
DF (Data Format) Bit—The
DF bit controls the format of
the input data, shown in hexadecimal (either Offset Two’s
Complement or Straight Binary), as shown:
Input Code
Offset Two's
Complement
DF = 0
(default)
8000
0000
7FFF
Straight
Binary
DF = 1
0000
8000
FFFF
V
OUT
0
V
REF
2 • V
REF
DISF (Disable Fast Settling) Bit—The
DISF bit disables
the fast settling option. If this bit is zero, the fast settling
performance is determined by the ADPT bit, the RES bit,
and the ADPT bit.
DISF
0
1
Fast Settling (default)
Disable Fast Settling
CALPIN (Calibration Pin) Bit—The
Calibration Pin bit
determines if the output is isolated or connected during
calibration.
CALPIN
0
1
Output Isolated
Output Connected
Default
SH (Sample/Hold) Bit —The
Sample-and-Hold bit deter-
mines if C
2
is internally connected to V
REF
. For best perfor-
mance, it is recommended to set this bit to 1.
SH
0
1
Disconnected
Connected
Default
Recommended
BD (Byte Order) Bit—The
BD bit controls the order in
which bytes of data are transferred (either most significant
byte first (MSBF) or least significant byte first (LSBF)), as
shown:
BD bit:
0 (default)
read
write only
MSBF
MSBF
MSBF
MSBF
write only
LSBF
LSBF
LSBF
LSBF
MSBF
MSBF
MSBF
MSBF
MSBF
1
0 (default)
write
MSBF
MSBF
LSBF
LSBF
LSBF
1
register
INSR
CMR
DIR
OCR
FCR
CRST (Calibration Reset) Bit—The
CRST bit resets the
offset and full-scale calibration registers.
CRST
0
1
OFF
Reset
Default
Care must be observed in reading the Command Register if
the state of the BD bit is unknown. If a two byte read is
started at address 0100 with BD = 0, it will read the contents
at address 0100, then 0101. However, if BD = 1, it will read
from 0100, then 0011. If the BD bit is unknown, all reads of
the command register are best performed as read commands
of one byte.
®
DAC1220
8
BURR-BROWN [ BURR-BROWN CORPORATION ]
