t3
t4
t5
tXIN
SCLK
SDIO
t1
t2
t6
t7
XIN
t8
FIGURE 5. XIN Clock Timing.
FIGURE 6. Serial Input/Output Timing.
t9
t14
SCLK
SDIO
SDIO
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
Write Register Data
IN0
OUTM
OUT1 OUT0
IN7
Read Register Data
FIGURE 7. Serial Interface Timing (CS LOW).
t15
CS
t10
t10
t9
SCLK
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
SDIO
SDIO
Write Register Data
IN0
OUTM
OUT1 OUT0
IN7
Read Register Data
FIGURE 8. Serial Interface Timing (using CS).
CS
t11
t12
t10
SCLK
t13
IN7
IN0
OUT MSB
OUT0
SDIO
t9
SDIO is an input
SDIO is an output
FIGURE 9. SDIO Input to Output Transition Timing.
®
12
DAC1220