Using CS
TIMING
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other. The CS
signal does not directly control the tri-state condition of the
SDIO output. These signals are normally in the tri-state
condition. They only become active when serial data is
being transmitted from the DAC1220. If the DAC1220 is in
the middle of a serial transfer and the SDIO is an output,
taking CS HIGH will not tri-state the output signal.
The maximum serial clock frequency cannot exceed the
DAC1220 XIN frequency divided by 10. Table IX and
Figures 5 through 9 define the basic digital timing character-
istics of the DAC1220. Figure 5 and the associated timing
symbols apply to the XIN input signal. Figures 6 through 9
and associated timing symbols apply to the serial interface
signals (SCLK, SDIO, and CS). The serial interface is
discussed in detail in the Serial Interface section.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, the CS signal must be used. The CS
signal is then used to enable communication with the
DAC1220.
SYMBOL
DESCRIPTION
MIN
NOM
MAX
UNITS
fXIN
tXIN
t1
XIN Clock Frequency
XIN Clock Period
1
400
2.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
XIN Clock High
0.4 • tXIN
0.4 • tXIN
5 • tXIN
5 • tXIN
40
t2
XIN Clock LOW
t3
SCLK HIGH
t4
SCLK LOW
t5
Data In Valid to SCLK Falling Edge (Setup)
SCLK Falling Edge to Data In Not Valid (Hold)
Data Out Valid After Rising Edge of SCLK (Hold)
SCLK Rising Edge to New Data Out Valid (Delay)(1)
t6
20
t7
0
t8
50
t9
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data
13 • tXIN
ns
ns
t10
t11
t12
t13
t14
Falling Edge of CS to Rising Edge of SCLK
Falling Edge of Last SCLK for INSR to SDIO as Output
SDIO as Output to Rising Edge of First SCLK for Register Data
Falling Edge of Last SCLK for Register Data to SDIO Tri-State
11 • tXIN
8 • tXIN
ns
ns
ns
ns
ns
10 • tXIN
6 • tXIN
4 • tXIN
4 • tXIN
Falling Edge of Last SCLK for Register Data to Rising Edge
of First SCLK of next INSR (CS Tied LOW)
41 • tXIN
t15
Rising Edge of CS to Falling Edge of CS (Using CS)
22 • tXIN
ns
NOTE: (1) With 10pF load.
TABLE IX. Digital Timing Characteristics.
®
11
BB [ BURR-BROWN CORPORATION ]
