with the peak of the bell curve representing the nominal code
for the input value. The ±1σ, ±2σ, and ±3σ distributions will
respectively represent the 68.3%, 95.5%, and 99.7% of all
codes. The transition noise can be calculated by dividing the
number of codes measured by six and this will yield the ±3σ
distribution, or 99.7%, of all codes. Statistically, up to three
codes could fall outside the distribution when executing
1,000 conversions. The ADS8322, with five output codes
for the ±3σ distribution, will yield a < ±0.8LSB transition
noise at 5V operation. Remember that to achieve this low-
noise performance, the peak-to-peak noise of the input
signal and reference must be < 50µV.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, during any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, or nearby digital logic or high-power de-
vices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.
AVERAGING
On average, the ADS8322 draws very little current from an
external reference, as the reference voltage is internally
buffered. If the reference voltage is external and originates
from an op amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation.
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conver-
sion results will reduce the transition noise by 1/2 to ±0.25
LSBs. Averaging should only be used for input signals with
frequencies near DC.
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the “analog” ground.
Avoid connections which are too close to the grounding point
of a microcontroller or digital signal processor. If required, run
a ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog cir-
cuitry.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging: for every decimation by 2, the
signal-to-noise ratio will improve 3dB.
As with the GND connections, VDD should be connected to
a +5V power supply plane, or trace, that is separate from the
connection for digital logic until they are connected at the
power entry point. Power to the ADS8322 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low-pass filter a noisy supply. In some situations, addi-
tional bypassing may be required, such as a 100µF electro-
lytic capacitor, or even a “Pi” filter made up of inductors and
capacitors—all designed to essentially lowpass filter the
+5V supply, removing the high-frequency noise.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8322 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
As the ADS8322 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to achieve good
performance from the converter.
ADS8322
SBAS215
9
BB [ BURR-BROWN CORPORATION ]
