TIMING DIAGRAM
t1
t3
t2
CLOCK
1
2
3
4
5
17
18
19
20
1
2
3
4
17
18
19
20
Acquisition
Conversion
tCONV
Acquisition
tACQ
t5
t4
CONVST
t6
t9
t10
BUSY
BYTE
t7
t11
t8
t12
CS
RD
t18
t13
t14
t15
t16
t17
t19
DB15-D8
DB7-D0
Bits 15-8
Bits 7-0
Bits 15-8
Bits 7-0
FF
Bits 15-8
(1)(2)
TIMING CHARACTERISTICS
All specifications typical at –40°C to +85°C, +VD = +5V.
ADS8322A
TYP
ADS8322B
TYP
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Conversion Time
Acquisition Time
CLOCK Period
CLOCK High Time
tCONV
tACQ
t1
t2
t3
t4
t5
t6
t7
1.6
0.4
ꢀ
ꢀ
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
40
40
10
5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CLOCK Low Time
CONVST Low to Clock High
CLOCK High to CONVST High
CONVST Low Time
CONVST Low to BUSY High
CS Low to CONVST Low
CONVST High
CLOCK Low to CONVST Low
CLOCK High to BUSY Low
CS High
CS Low to RD Low
RD High to CS High
RD Low Time
RD Low to Data Valid
Data Hold from RD High
BYTE Change to RD Low(3)
RD High Time
20
25
25
ꢀ
ꢀ
t8
t9
0
20
0
ꢀ
ꢀ
ꢀ
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
0
0
0
50
40
5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
20
NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See timing diagram, above.
(3) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BUSY is 1, bits 15 through 8 appear on DB7-DB0. RD may remain low
between changes in BYTE.
ADS8322
4
SBAS215
BB [ BURR-BROWN CORPORATION ]
