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ADS8322Y/2K 参数 Datasheet PDF下载

ADS8322Y/2K图片预览
型号: ADS8322Y/2K
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 500kHz的,微功耗采样模拟数字转换器 [16-Bit, 500kHz, MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 10 页 / 204 K
品牌: BB [ BURR-BROWN CORPORATION ]
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REFERENCE  
THEORY OF OPERATION  
Under normal operation, the REFOUT pin should be directly  
connected to the REFIN pin to provide an internal +2.5V  
reference to the ADS8322. The ADS8322 can operate,  
however, with an external reference in the range of 1.5V to  
2.6V for a corresponding full-scale range of 3.0V to 5.2V.  
The ADS8322 is a high-speed Successive Approximation  
Register (SAR) A/D converter with an internal 2.5V bandgap  
reference. The architecture is based on capacitive redistribu-  
tion which inherently includes a sample-and-hold function.  
The basic operating circuit for the ADS8322 is shown in  
Figure 1.  
The internal reference of the ADS8322 is double-buffered.  
If the internal reference is used to drive an external load, a  
buffer is provided between the reference and the load ap-  
plied to the REFOUT pin (the internal reference can typically  
source and sink 10µA of current). If an external reference is  
used, the second buffer provides isolation between the exter-  
nal reference and the CDAC. This buffer is also used to  
recharge all of the CDAC capacitors during conversion.  
The ADS8322 requires an external clock to run the conver-  
sion process. The clock can be run continuously or it can be  
gated to conserve power between conversions. This clock  
can vary between 25kHz (1.25kHz throughput) and 10MHz  
(500kHz throughput). The duty cycle of the clock is unim-  
portant as long as the minimum HIGH and LOW times are  
at least 40ns and the clock period is at least 100ns. The  
minimum clock frequency is governed by the parasitic  
leakage of the Capacitive Digital-to-Analog (CDAC) ca-  
pacitors internal to the ADS8322.  
ANALOG INPUT  
When the converter enters Hold mode, the voltage differ-  
ence between the +IN and –IN inputs is captured on the  
internal capacitor array. The voltage on the –IN input is  
The analog input is provided to two input pins, +IN and –IN.  
When a conversion is initiated, the differential input on these  
pins is sampled on the internal capacitor array. While a  
conversion is in progress, both inputs are disconnected from  
any internal function.  
+5V Analog Supply  
10µF  
+
0.1µF  
+
0.1µF  
Analog Input  
32 31 30 29 28 27 26 25  
Chip Select  
1
2
3
4
5
6
7
8
DB15  
DB14  
DB13  
DB12  
DB11  
DB10  
DB9  
CS 24  
BYTE 23  
RD 22  
Read Input  
Conversion Start  
Clock Input  
CONVST 21  
CLOCK 20  
DGND 19  
+VD 18  
ADS8322  
Busy Output  
DB8  
BUSY 17  
9
10 11 12 13 14 15 16  
FIGURE 1. Typical Circuit Configuration.  
ADS8322  
SBAS215  
7