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ADS7863IDBQ 参数 Datasheet PDF下载

ADS7863IDBQ图片预览
型号: ADS7863IDBQ
PDF下载: 下载PDF文件 查看货源
内容描述: 双路, 1.5MSPS , 12位, 2 + 2通道,同步采样模拟数字转换器 [Dual, 1.5MSPS, 12-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器光电二极管
文件页数/大小: 30 页 / 663 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS7863  
www.ti.com  
SBAS383JUNE 2007  
Power-Down  
Modes and  
Reset  
In nap power-down mode, the ADS7863 turns off  
the biasing of the comparator and the mid-voltage  
buffer. In this mode, power dissipation reduces to  
approximately 0.3mA within 200ns. The device goes  
into nap power-down mode regardless of the  
conversion state.  
(Not ADS7861-Compatible)  
The ADS7863 has  
a
comprehensive built-in  
power-down feature. There are three power-down  
modes: deep power-down, nap power-down, and  
auto-nap power-down. All three power-down modes  
are activated with the 12th falling CLOCK edge of  
the SDI access, during which the related bit asserts  
(DP = '1', N = '1', or AN = '1'). All modes are  
deactivated by de-asserting the respective bit in the  
SDI Register. Contents of the SDI Register are not  
affected by any of the power-down modes. Any  
ongoing conversion aborts when deep or nap  
power-down is initiated. Table 8 lists the differences  
among the three power-down modes.  
The auto-nap power-down mode is almost identical  
to the nap mode. The only difference is the time  
required to power down and the method of waking  
up the device. The SDI Register bit AN is only used  
to enable/disable this feature. If the auto-nap mode  
is enabled, the ADS7863 turns off the biasing  
automatically after finishing a conversion; thus, the  
end of conversion actually activates the auto-nap  
power-down. Device power dissipation reduces to  
about 0.3mA within 200ns in this mode, as well.  
Triggering a new conversion by applying a CONVST  
pulse puts the device back into normal operation.  
In deep power-down mode, all functional blocks  
except the digital interface are disabled. The analog  
block has its bias currents and the internal oscillator  
turned off. In this mode, the power dissipation  
reduces to 1μA within 2μs. The wake-up time from  
deep power-down mode is 1μs.  
To issue a device reset, an RD pulse must be  
generated along with an SDI word containing A[2:0]  
= '101'. With the 12th falling edge after generating  
the RD pulse, the entire device—including the serial  
interface—is forced into reset. After approximately  
20ns, the serial interface becomes active again.  
Table 8. Power-Down Modes  
POWER-  
DOWN TYPE DISSIPATION  
POWER  
ENABLED  
BY  
ACTIVATED  
BY  
ACTIVATION  
TIME  
RESUMED  
BY  
REACTIVATION  
TIME  
DISABLED  
BY  
Deep  
Nap  
1μA  
DP = ‘1’  
N = ‘1’  
12th clock  
12th clock  
2μs  
DP = ‘0’  
N = ‘0’  
1μs  
DP = ‘0’  
N = ‘0’  
300μA  
200ns  
3 clocks  
Each end of  
conversion  
Auto-nap  
300μA  
AN = ‘1’  
200ns  
CONVST pulse  
3 clocks  
AN = ‘0’  
23  
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