ADS7863
www.ti.com
SBAS383–JUNE 2007
Programming the Reference DAC
(Not ADS7861-Compatible)
read access. Triggering the RD line again causes the
SDOA output to send '0000' followed by the 10-bit
DAC value and another '00'. During the second RD
access, data present on SDI are ignored, while in
Mode I and Mode III valid conversion data for
channel B are present on SDOB. The default value
of the DAC register after power-up is 0x3FF,
corresponding to a reference voltage of 2.5V on the
REFOUT pin.
The internal reference DAC can be set by issuing an
RD pulse while providing an SDI word with P[1:0] =
'01' and A[2:0] = '001'. Thereafter, a second RD
pulse must be generated with an SDI word starting
with '00' followed by the actual 10-bit DAC value (see
Figure 24). During the second access, the first two
'00' bits are not interpreted as channel selection bits.
To verify the DAC setting, an RD pulse must be
generated while providing an SDI word containing
P[1:0] = '01' and A[2:0] = '011' to initialize the DAC
16
1
16
1
16
1
16
1
16
1
1
1
CLOCK
CONVST
10-Bit
SDI
DAC Value
C[1:0] = '00' ® CHx0 is Next
P[1:0] = '01' ® Features ON
A[2:0] = '001' ® Write DAC
C[1:0] = '11' ® CHx1 is Next
P[1:0] = '01' ® Features ON
A[2:0] = '011' ® Read DAC
Data Interpreted as
DAC Value Only
C[1:0] = '00' ® CHx0 is Next C[1:0] = '00' ® CHx0 is Next
SDI Data Ignored
P[1:0] = '11' ® No Features
P[1:0] = '11' ® No Features
M0
M1
RD
CS
Previous 12-Bit
Data CHAx
12-Bit
Data CHA0
12-Bit
Data CHA0
10-Bit
DAC Value
12-Bit
Data CHA1
12-Bit
Data CHA0
SDOA
Previous 12-Bit
Data CHBx
12-Bi
Data CHB0
12-Bit
Data CHB0
12-Bit
Data CHB1
12-Bit
Data CHB1
12-Bit
Data CHB0
SDOB
BUSY
Previous Conversion
of Both CHxx
Conversion of
Both CHx0
Conversion of
Both CHx0
Conversion of
Both CHx1
Conversion of
Both CHx1
Conversion of
Both CHx0
0ms
0.5ms
1.0ms
1.5ms
2.0ms
2.5ms
3.0ms
Figure 24. DAC Write and Read Access Timing Diagram
22
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