ADS7863
www.ti.com
SBAS383–JUNE 2007
LAYOUT
underneath (or next) to the ADC. Otherwise, even
short undershoots on the digital interface with a
value lower than –300mV will lead to conduction of
ESD diodes, causing current flow through the
substrate and degrading the analog performance.
For optimum performance, care should be taken with
the physical layout of the ADS7863 circuitry. This
condition is particularly true if the CLOCK input is
approaching the maximum throughput rate. The
basic SAR architecture is quite sensitive to glitches
or sudden changes on the power supply, reference,
ground connections, and digital inputs that occur just
prior to latching the output of the analog comparator.
Therefore, driving any single conversion for an n-bit
SAR converter, there are n windows in which large
external transient voltages can affect the conversion
result. Such glitches might originate from switching
power supplies, nearby digital logic, or high-power
devices. The degree of error in the digital output
depends on the reference voltage, layout, and the
exact timing of the external event. These errors can
change if the external event also changes in time
with respect to the CLOCK input.
During the PCB layout, care should also be taken to
avoid any return currents crossing any sensitive
analog areas or signals. No signal must exceed the
limit of –300mV with respect to the according ground
plane.
Supply
The ADS7863 has two separate supplies, the BVDD
pin for the digital interface and the AVDD pin for all
remaining (analog) circuits.
BVDD can range from 1.65V to 5.5V, allowing the
ADS7863 to interface with all state-of-the-art
processors and controllers. To limit the injection of
noise energy from external digital circuitry, BVDD
should be filtered properly. Bypass capacitors of
0.1μF and 10μF should be placed between the BVDD
pin and the ground plane.
With this possibility in mind, power to the ADS7863
should be clean and well-bypassed. A 0.1μF ceramic
bypass capacitor should be placed as close to the
device as possible. In addition, a 1μF to 10μF
capacitor is recommended. If needed, an even larger
capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
AVDD is used to supply the internal analog circuitry.
For optimum performance, a linear regulator (for
example, the UA7805 family) is recommended to
generate the analog supply voltage in the range of
2.7V to 5.5V for the ADS7863 and the necessary
analog front-end circuitry.
If the reference voltage is external and originates
from an operational amplifier, be sure that it can
drive the bypass capacitor or capacitors without
oscillation.
Bypass capacitors should be connected to the
ground plane such that the current is allowed to flow
through the pad of the capacitor (that is, the vias
should be placed on the opposite side of the
connection between the capacitor and the
power-supply pin of the ADC).
Grounding
The xGND pins should be connected to a clean
ground reference. These connections should be kept
as short as possible to minimize the inductance of its
path. It is recommended to use vias connecting the
pads directly to the ground plane. In designs without
ground planes, the ground trace should be kept as
wide as possible. Avoid connections that are too
near the grounding point of a microcontroller or
digital signal processor.
Digital Interface
To further optimize device performance, a resistor of
10Ω to 100Ω can be used on each digital pin of the
ADS7863. In this way, the slew rate of the input and
output signals is reduced, limiting the noise injection
from the digital interface.
Depending on the circuit density on the board,
placement of the analog and digital components, and
the related current loops, a single solid ground plane
for the entire printed circuit board (PCB) or a
dedicated analog ground area may be used. In an
instance of a separated analog ground area, ensure
a low-impedance connection between the analog
and digital ground of the ADC by placing a bridge
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