Keep in mind that the time period when the comparator is
most sensitive to noise is fairly small. Also, the peak portion
of the noise “event” produced by a digital transition is fairly
brief as most digital signals transition in a few nanoseconds.
The subsequent noise may last for a period of time longer
than this and may induce further effects which require a
longer settling time; however, in general, the event is over
within a few tens of nanoseconds.
three converters. After the conversions are finished, each
result is transferred, in turn. The QSPI port is completely
programmable to handle the timing and transfers without
processor intervention. If the CONV signal is generated in
this way, it should be possible to make both AC and DC
measurements with the ADS7812, as the CONV signal will
have low jitter. Note that if the CONV signal is generated via
software commands, it will have a good deal of jitter and
only low frequency (DC) measurements can be made.
For the ADS7812, error correction is done when the tenth bit
is decided. During this bit decision, it is possible to correct
limited errors that may have occurred during previous bit
decisions. However, after the tenth bit, no such correction is
possible. Note that for the timing diagrams shown in Figures
2, 5, 6, 7, and 8, all external digital signals should remain
static from 8µs after the start of a conversion until BUSY
rises. The tenth bit is decided approximately 10µs to 11µs
into the conversion.
QSPI
ADS7812
CONV EXT/INT
+5V
PCS0
PCS1
PCS2
PCS3
SCK
CS
DATACLK
DATA
MIS0
APPLICATIONS INFORMATION
+5V
ADS7812
QSPI INTERFACING
CONV
CS
EXT/INT
Figure 14 shows a simple interface between the ADS7812
and any queued serial peripheral interface (QSPI) equipped
microcontroller (available on several Motorola devices).
This interface assumes that the convert pulse does not
originate from the microcontroller and that the ADS7812 is
the only serial peripheral.
DATACLK
DATA
+5V
ADS7812
Before enabling the QSPI interface, the microcontroller must
be configured to monitor the slave select (SS) line. When a
LOW to HIGH transition occurs (indicating the end of a
conversion), the port can be enabled. If this is not done, the
microcontroller and A/D converter may not be properly syn-
chronized. (The slave select line simply enables communica-
tion—it does not indicate the start or end of a serial transfer.)
CONV
CS
EXT/INT
DATACLK
DATA
FIGURE 15. QSPI Interface to the Three ADS7812s.
DSP56002 INTERFACING
Convert Pulse
The DSP56002 serial interface has an serial peripheral
interface (SPI) compatibility mode with some enhance-
ments. Figure 16 shows an interface between the ADS7812
and the DSP56002. As with the QSPI interface of Figure 14,
QSPI
ADS7812
CONV
Convert Pulse
PCS0/SS
MOSI
BUSY
DATA
DSP56002
ADS7812
SCK
DATACLK
CS
CONV
SC1
BUSY
EXT/INT
SRD
SCO
DATA
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.
DATACLK
CS
FIGURE 14. QSPI Interface to the ADS7812.
EXT/INT
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
Figure 15 shows a QSPI-equipped microcontroller interfac-
ing to three ADS7812s. There are many possible variations
to this interface scheme. As shown, the QSPI port produces
a common CONV signal which initiates a conversion on all
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
FIGURE 16. DSP56002 Interface to the ADS7812.
®
ADS7812
16
BB [ BURR-BROWN CORPORATION ]
