External DATACLK Active After the Conversion
might be possible to use the rising edge of the DATACLK
signal. However, one extra clock period (not shown in
Figures 6, 7, and 8) is needed for the final bit.
The preferred method of obtaining the conversion result is to
provide the DATACLK signal after the conversion has been
completed and before the next conversion starts—as shown
in Figure 6. Note that the DATACLK signal should be static
before the start of the next conversion. If this is not ob-
served, the DATACLK signal could affect the voltage that
is acquired.
The external DATACLK signal must be LOW or CS must
be HIGH prior to BUSY rising (see time t25 in Figures 7 and
8). If this is not observed, the output shift register of the
ADS7812 will not be updated with the conversion result.
Instead, the previous contents of the shift register will
remain and the new result will be lost.
External DATACLK Active During the Next Conversion
If more than 12 clock cycles are provided to the DATACLK
input, the DATA output will go LOW after the rising edge
of the 13th clock period. The operation of the ADS7812 will
not be affected as long as the timing specifications are met.
Another method of obtaining the conversion result is shown
in Figure 7. Since the output shift register is not updated until
the end of the conversion, the previous result remains valid
during the next conversion. If a fast clock (≥ 2MHz) can be
provided to the ADS7812, the result can be read during time
t2. During this time, the noise from the DATACLK signal is
less likely to affect the conversion result.
Before reading the next three paragraphs, consult the Sensi-
tivity to External Digital Signals section of this data sheet.
This will explain many of the concerns regarding how and
when to apply the external DATACLK signal.
t1
t2
CONV
BUSY
t21
t24
t23
t25
DATACLK
DATA
1
2
3
4
11
12
1
t19
t20
t22
MSB
Bit 10
Bit 9
Bit 1
LSB
MSB
FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,
CS LOW).
CONV
BUSY
t5
t4
t24
t25
DATACLK
DATA
1
2
n
n+1
11
12
Bit n-1
MSB
Bit 10
Bit n
Bit 1
LSB
FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion
(EXT/INT HIGH, CS LOW).
®
11
ADS7812
BB [ BURR-BROWN CORPORATION ]
