For example, the timing diagram in Figure 2 shows that the
CONV signal should return HIGH sometime during time t2.
In fact, the CONV signal can return HIGH at any time
during the conversion. However, after time t2, the transition
of the CONV signal has the potential of creating a good deal
of noise on the ADS7812 die. If this transition occurs at just
precisely the wrong time, the conversion results could be
affected. In a similar manner, transitions on the DATACLK
input could affect the conversion result.
LAYOUT
The ADS7812 should be treated as a precision analog
component and should reside completely on the “analog”
portion of the printed circuit board. Ideally, a ground plane
should extend underneath the ADS7812 and under all other
analog components. This plane should be separate from the
digital ground until they are joined at the power supply
connection. This will help prevent dynamic digital ground
currents from modulating the analog ground through a
common impedance to power ground.
For the ADS7812, there are 12 separate bit decisions which
are made during the conversion. The most significant bit
decision is made first, proceeding to the least significant bit
at the end of the conversion. Each bit decision involves the
assumption that the bit being tested should be set. This is
combined with the result that has been achieved so far. The
converter compares this combined result with the actual
input voltage. If the combined result is too high, the bit is
cleared. If the result is equal to or lower than the actual input
voltage, the bit remains HIGH. This is why the basic
architecture is referred to as “successive approximation
register.”
The +5V power should be clean, well-regulated, and sepa-
rate from the +5V power for the digital portion of the design.
One possibility is to derive the +5V supply from a linear
regulator located near the ADS7812. If derived from the
digital +5V power, a 5Ω to 10Ω resistor should be placed in
series with the power connection from the digital supply. It
may also be necessary to increase the bypass capacitance
near the VS pin (an additional 100µF or greater capacitor in
parallel with the 10µF and 0.1µF capacitors). For designs
with a large number of digital components or very high
speed digital logic, this simple power supply filtering scheme
may not be adequate.
If the result so far is getting very close to the actual input
voltage, then the comparison involves two voltages which are
very close together. The ADS7812 has been designed so that
the internal noise sources are a minimum just prior to the
comparator result being latched. However, if a external digital
signal transitions at this time, a great deal of noise will be
coupled into the sensitive analog section of the ADS7812.
Even if this noise produces a difference between the two
voltages of only 2mV, the conversion result will be off by 3
counts or least significant bits (LSBs). (The internal LSB size
of the ADS7812 is 610µV regardless of the input range.)
SENSITIVITY TO EXTERNAL
DIGITAL SIGNALS
All successive approximation register-based A/D converters
are sensitive to external sources of noise. The reason for this
will be explained in the following paragraphs. For the
ADS7812 and similar A/D converters, this noise most often
originates due to the transition of external digital signals.
While digital signals that run near the converter can be the
source of the noise, the biggest problem occurs with the
digital inputs to the converter itself.
Once a digital transition has caused the comparator to make
a wrong bit decision, the decision cannot be corrected. All
subsequent bit decisions will then be wrong (unless some
type of error correction is employed). Figure 13 shows a
successive approximation process that has gone awry. The
dashed line represents what the correct bit decisions should
have been. The solid line represents the actual result of the
conversion.
In many cases, the system designer may not be aware that
there is a problem or a potential for a problem. For a 12-bit
system, these problems typically occur at the least significant
bits and only at certain places in the converter’s transfer
function. For a 16-bit converter, the problem can be much
easier to spot.
External Noise
SAR Operation after
Wrong Bit Decision
Actual Input
Voltage
Converter’s
Full-Scale
Input Voltage
Range
Proper SAR Operation
Internal DAC
Voltage
Wrong Bit Decision Made Here
t
Conversion Clock
1
1
0
0
1
0
1
0
0
0
Incorrect Result
Correct Result
Conversion Start
(Hold Mode)
(1
1)
FIGURE 13. SAR Operation When External Noise Affects the Conversion.
15
®
ADS7812
BB [ BURR-BROWN CORPORATION ]
