SPI INTERFACE
the pulse width is (0.7)RC. Choosing a pulse width as close
to the minimum value specified in this data sheet will offer
the best performance. See the Starting A Conversion sec-
tion of this data sheet for details on the conversion pulse
width.
The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 12. The
microcontroller will need to fetch the 8 most significant bits
before the contents are overwritten by the least significant
bits.
The maximum conversion rate for a 20.48MHz DSP56000
is 35.6kHz. If a slower oscillator can be tolerated on the
DSP56000, a conversion rate of 40kHz can be achieved by
using a 19.2MHz clock and a prescale modulus of four.
A modified version of the QSPI interface shown in Figure 13
might be possible. For most microcontrollers with SPI inter-
face, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications
due to the insufficient jitter performance of the convert pulse
itself.
Convert Pulse
DSP56000
ADS7806
R/C
DSP56000 INTERFACING
SC1
BUSY
The DSP56000 serial interface has an SPI compatibility
mode with some enhancements. Figure 14 shows an inter-
face between the ADS7806 and the DSP56000 which is very
similar to the QSPI interface seen in Figure 12. As men-
tioned in the QSPI section, the DSP56000 must be pro-
grammed to enable the interface when a LOW to HIGH
transition on SC1 is observed (BUSY going HIGH at the end
of conversion).
SRD
SCO
SDATA
DATACLK
CS
EXT/INT
BYTE
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD1 = 0 (SC1 is an input)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 12 bits)
The DSP56000 can also provide the convert pulse by includ-
ing a monostable multi-vibrator as seen in Figure 15. The
receive and transmit sections of the interface are decoupled
(asynchronous mode) and the transmit section is set to
generate a word length frame sync every other transmit
frame (frame rate divider set to two). The prescale modulus
should be set to five.
FIGURE 14. DSP56000 Interface to the ADS7806.
The monostable multi-vibrator in this circuit will provide
varying pulse widths for the convert pulse. The pulse width
will be determined by the external R and C values used with
the multi-vibrator. The 74HCT123N data sheet shows that
74HCT123N
+5V
+5V
DSP56000
R
B1
REXT1
C
ADS7806
SC2
CLR1
A1
CEXT1
Q1
R/C
SC0
SRD
DATACLK
SDATA
CS
EXT/INT
BYTE
SYN = 0 (Asychronous)
GCK = 1 (Gated clock)
SCD2 = 1 (SC2 is an output)
SHFD = 0 (Shift MSB first)
WL1 = 0 WL0 = 1 (Word length = 16 bits)
FIGURE 15. DSP56000 Interface to the ADS7806. Processor Initiates Conversions.
®
ADS7806
18
BB [ BURR-BROWN CORPORATION ]
