SERIAL OUTPUT
INTERNAL DATA CLOCK (During A Conversion)
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful
with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as
these pins will come out of Hi-Z state whenever CS (pin 23)
is LOW and R/C (pin 22) is HIGH. The serial output can not
be tri-stated and is always active.
To use the internal data clock, tie EXT/INT (pin 8) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7806 will output 12
bits of valid data, MSB first, from conversion ‘n-1’ on
SDATA (pin 19), synchronized to 12 clock pulses output on
DATACLK (pin 18). The data will be valid on both the
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 12th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to what-
ever logic level was input on TAG (pin 20) during the first
clock pulse. Refer to Table VI and Figure 4.
SYMBOL
DESCRIPTION
Convert Pulse Width
MIN TYP MAX UNITS
t1
t2
t3
0.04
12
14.7 20
85
µs
µs
ns
Data Valid Delay after R/C LOW
BUSY Delay from
Start of Conversion
t4
t5
BUSY LOW
14.7 20
90
µs
BUSY Delay after
End of Conversion
ns
EXTERNAL DATA CLOCK
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7806, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
t6
t7
Aperture Delay
Conversion Time
40
ns
µs
µs
ns
ns
µs
14.7 20
t8
Acquisition Time
5
83
t9
Bus Relinquish Time
BUSY Delay after Data Valid
10
20
t10
t11
60
Previous Data Valid
after Start of Conversion
12 14.7
t12
t13
Bus Access Time and BYTE Delay
83
ns
Start of Conversion
to DATACLK Delay
1.4
1.1
µs
An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions. While this is
perfectly acceptable, there is a possible problem when using
an external data clock. At an indeterminate point from 12µs
after the start of conversion 'n' until BUSY rises, the internal
logic will shift the results of conversion 'n' into the output
register. If CS is LOW, R/C is HIGH, and the external clock
is HIGH at this point, data will be lost. So, with CS LOW,
either R/C and/or DATACLK must be LOW during this
period to avoid losing valid data.
t14
t15
DATACLK Period
µs
Data Valid to DATACLK
HIGH Delay
20
75
ns
t16
Data Valid after DATACLK
LOW Delay
400 600
ns
t17
t18
t19
t20
External DATACLK Period
External DATACLK LOW
External DATACLK HIGH
100
40
ns
ns
ns
ns
50
CS and R/C to External
DATACLK Setup Time
25
t21
t22
R/C to CS Setup Time
Valid Data after DATACLK HIGH
Throughput Time
10
25
ns
ns
µs
t7 + t8
25
TABLE VI. Conversion and Data Timing. TA = –40°C to
+85°C.
t7 + t8
CS or R/C(1)
t14
1
2
3
11
12
1
2
t13
DATACLK
t16
t15
MSB Valid
Bit 10 Valid
Bit 9 Valid
Bit 1 Valid
LSB Valid
MSB Valid
Bit 10 Valid
SDATA
BUSY
(Results from previous conversion.)
NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
®
ADS7806
10
BB [ BURR-BROWN CORPORATION ]
