used for each input range (see Figure 8). The input resistor
divider network provides inherent overvoltage protection
guaranteed to at least ±25V.
OFFSET ADJUST
RANGE (mV)
GAIN ADJUST
RANGE (mV)
INPUT RANGE
±10V
±15
±4
±60
±30
±30
Analog inputs above or below the expected range will yield
either positive full scale or negative full scale digital outputs
respectively. There will be no wrapping or folding over for
analog inputs outside the nominal range.
0 to 5V
0 to 4V
±3
TABLE VII. Offset and Gain Adjust Ranges for Hardware
Calibration (see Figure 7a).
fications for offset and gain, the resistors shown in Figure 7b
are necessary. See the No Calibration section for more
details on the external resistors. Refer to Table VIII for the
range of offset and gain errors with and without the external
resistors.
CALIBRATION
HARDWARE CALIBRATION
To calibrate the offset and gain of the ADS7806 in hard-
ware, install the resistors shown in Figure 7a. Table VII lists
the hardware trim ranges relative to the input for each input
range.
NO CALIBRATION
See Figure 7b for circuit connections. Note that the actual
voltage dropped across the external resistors is at least two
orders of magnitude lower than the voltage dropped across
the internal resistor divider network. This should be consid-
SOFTWARE CALIBRATION
To calibrate the offset and gain in software, no external
resistors are required. However, to get the data sheet speci-
±10V
0-5V
0-4V
33.2kΩ
200Ω
1
2
3
4
5
6
200Ω
1
R1IN
VIN
R1IN
1
2
3
4
5
6
R1IN
2
3
4
5
6
200Ω
AGND1
R2IN
33.2kΩ
AGND1
R2IN
VIN
AGND1
R2IN
VIN
100Ω
50kΩ
100Ω
+5V
CAP
33.2kΩ
100Ω
+
+
+5V
+5V
2.2µF
2.2µF
CAP
+
+
2.2µF
CAP
+
+
50kΩ
REF
50kΩ
2.2µF
50kΩ
1MΩ
REF
50kΩ
+5V
REF
AGND2
1MΩ
2.2µF
50kΩ
1MΩ
2.2µF
AGND2
AGND2
FIGURE 7a. Circuit Diagrams (With Hardware Trim).
±10V
0-5V
0-4V
200Ω
1
200Ω
33.2kΩ
VIN
R1IN
1
R1IN
2
3
4
5
6
1
2
3
4
5
6
AGND1
R2IN
2
3
4
5
6
R1IN
33.2kΩ
AGND1
R2IN
200Ω
66.5kΩ
+5V
VIN
AGND1
R2IN
VIN
100Ω
100Ω
CAP
+
+
CAP
2.2µF
2.2µF
+
+
2.2µF
100Ω
REF
CAP
REF
+
+
2.2µF
2.2µF
AGND2
REF
AGND2
2.2µF
AGND2
FIGURE 7b. Circuit Diagrams (Without Hardware Trim).
®
ADS7806
13