The resistive front end of the ADS7806 also provides a
guaranteed ±25V overvoltage protection. In most cases, this
eliminates the need for external over voltage protection
circuitry.
bus. This interface and the following discussion assume a
master clock for the QSPI interface of 16.78MHz. Notice
that the serial data input of the microcontroller is tied to the
MSB (D7) of the ADS7806 instead of the serial output
(SDATA). Using D7 instead of the serial port offers tri-state
capability which allows other peripherals to be connected to
the MISO pin. When communication is desired with those
peripherals, PCS0 and PCS1 should be left HIGH; that will
keep D7 tri-stated and prevent a conversion from taking
place.
INTERMEDIATE LATCHES
The ADS7806 does have tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversion, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
In this configuration, the QSPI interface is actually set to do
two different serial transfers. The first, an eight bit transfer,
causes PCS0 (R/C) and PCS1 (CS) to go LOW starting a
conversion. The second, a twelve bit transfer, causes only
PCS1 (CS) to go LOW. This is when the valid data will be
transferred.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7806 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance. The effects of this phenomenon will
be more obvious when using the pin-compatible ADS7807
or any of the other 16-bit converters in the ADS Family. This
is due to the smaller internal LSB size of 38µV.
QSPI
ADS7806
+5V
R/C
CS
EXT/INT
PCS0
PCS1
SCK
DATACLK
D7 (MSB)
APPLICATIONS INFORMATION
MISO
QSPI INTERFACING
Figure 12 shows a simple interface between the ADS7806
and any QSPI equipped microcontroller. This interface as-
sumes that the convert pulse does not originate from the
microcontroller and that the ADS7806 is the only serial
peripheral.
BYTE
CPOL = 0
CPHA = 0
Before enabling the QSPI interface, the microcontroller
must be configured to monitor the slave select line. When a
transition from LOW to HIGH occurs on Slave Select (SS)
from BUSY (indicating the end of the current conversion),
the port can be enabled. If this is not done, the microcontroller
and the and the A/D may be “out-of-sync.”
FIGURE 13. QSPI Interface to the ADS7806. Processor
Initiates Conversions.
For both transfers, the DT register (delay after transfer) is
used to cause a 19µs delay. The interface is also set up to
wrap to the beginning of the queue. In this manner, the QSPI
is a state machine which generates the appropriate timing for
the ADS7806. This timing is thus locked to the crystal based
timing of the microcontroller and not interrupt driven. So,
this interface is appropriate for both AC and DC measure-
ments.
Figure 13 shows another interface between the ADS7806
and a QSPI equipped microcontroller. The interface allows
the microcontroller to give the convert pulses while also
allowing multiple peripherals to be connected to the serial
For the fastest conversion rate, the baud rate should be set to
two (4.19MHz SCK), DT set to ten, the first serial transfer
set to eight bits, the second set to twelve bits, and DSCK
disabled (in the command control byte). This will allow for
a 23kHz maximum conversion rate. For slower rates, DT
should be increased. Do not slow SCK as this may increase
the chance of affecting the conversion results or accidently
initiating a second conversion during the first eight bit
transfer.
In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the eight bit transfer should be set
to 20H and for the twelve bit transfer to 61H.
Convert Pulse
QSPI
ADS7806
R/C
PCS0/SS
MOSI
BUSY
SDATA
DATACLK
CS
SCK
EXT/INT
BYTE
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.
FIGURE 12. QSPI Interface to the ADS7806.
®
ADS7806
17
BB [ BURR-BROWN CORPORATION ]
