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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
SERIAL INTERFACE TIMING
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0. LVDS BUFFERS
0
0
1
1
0
1
0
1
Normal ADC Output
Deskew Pattern
Patterns Get Reversed in MSB First
Mode of LVDS
Sync Pattern
Custom Pattern
0
0
1
1
0
1
0
1
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
0
0
0
1
1. LSB/MSB MODE
D3
0
D2
X
D1
X
D0
1
2X LVDS Clock Input Current
LSB Mode
0
0
X
X
0
1
X
X
MSB Mode
0
0
0
0
1
1
0
1
2. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
X
X
X
X
3. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
X
X
X
X
CUSTOM PATTERN (registers 4-6)
D3
MSB
X
D2
X
D1
X
D0
X
0
0
0
1
1
1
0
0
1
0
1
0
X
X
X
Bits for Custom Pattern
X
X
X
LSB
(1)
TEST PATTERNS
Deskew
101010101010
000000111111
Sync
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6.
(1)
Default is LSB first. If MSB is selected the above patterns will be reversed.
6
BB [ BURR-BROWN CORPORATION ]
