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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
AC CHARACTERISTICS
T
= −40°C, T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −0.5dBFS, internal voltage reference, and 2V
differential input, unless otherwise noted.
PP
ADS5273
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DYNAMIC CHARACTERISTICS
f
f
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 1MHz
= 5MHz
= 10MHz
= 20MHz
= 10MHz
85
85
dBc
dBc
IN
IN
TBD
SFDR Spurious-Free Dynamic Range
f
f
85
dBc
IN
80
dBc
IN
f
f
90
dBc
IN
IN
TBD
TBD
TBD
TBD
87
dBc
HD
HD
2nd-Order Harmonic Distortion
3rd-Order Harmonic Distortion
2
f
f
80
dBc
IN
76
dBc
IN
f
f
87
dBc
IN
IN
84
dBc
3
f
f
77
dBc
IN
73
dBc
IN
f
f
70.5
70.5
70.5
70.5
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
SNR Signal-to-Noise Ratio
f
f
IN
IN
f
f
IN
IN
70
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
f
f
f
70
IN
IN
IN
70
11.3
Signal Applied to 7 Channels; Measurement Taken on the
Channel with No Input Signal
Crosstalk
−85
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at I = 3.5mA, R
O
= 100Ω, and C = 9pF. All LVDS specifications are characterized but not tested.
LOAD
LOAD
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS
V
Output Voltage High, OUT or OUT
R
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1340
1038
350
1475
mV
mV
mV
V
OH
P
N
LOAD
LOAD
V
Output Voltage Low, OUT or OUT
R
R
= 100Ω 1%
= 100Ω 1%
925
325
OL
P
N
LOAD
V
Output Differential Voltage
Output Offset Voltage
375
OD
LOAD
V
R
= 100Ω 1%; See LVDS Timing Diagram, Page 7
1.125
1.250
TBD
1.275
OS
R
∆R
C
Output Impedance, Single-Ended
V
V
V
= 1.0V and 1.4V
= 1.0V and 1.4V
= 1.0V and 1.4V
Ω
%
O
O
O
CM
CM
CM
Mismatch Between OUT and OUT
P
Output Capacitance
TBD
5
N
3
4
pF
mV
mV
∆V
Change in V Between 0 and 1
R
= 100Ω 1%
= 100Ω 1%
25
25
OD
OD
LOAD
LOAD
∆V
Change Between 0 and 1
R
OS
ISOUT ,
P
Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
ISOUT
N
ISOUT
Output Current
Drivers Shorted Together
12
10
mA
mA
NP
I , I
Power-Off Output Leakage
V
= 0V
XN XP
CC
DRIVER AC SPECIFICATIONS
Clock Clock Signal Duty Cycle
6 × ADCLK
45
50
55
50
%
tp
HLP
− tp
or tp
HLN
− tp ,
LHP
LHN
(1)
t
t
Any Differential Pair on Package
ps
SKEW1
Differential Skew
tp − tp
Channel-to-Channel Skew
,
DIFF[X] DIFF[Y]
(2)
Any Two Signals on Package
100
ps
SKEW2
(3)
t
/t
V
Rise Time or V Fall Time
Z
Z
Z
= 100Ω, C = 9pF, I = 2.5mA
400
250
200
150
RISE FALL
OD
OD
LOAD
LOAD
LOAD
I
O
= 100Ω, C = 9pF, I = 3.5mA
ps
ps
ps
I
O
= 100Ω, C = 9pF, I = 4.5mA
I
O
Z
= 100Ω, C = 9pF, I = 6mA
I O
LOAD
(1)
(2)
(3)
Skew measurements are made at the 50% point of the transition.
Skew measurements made at 0V differential (that is, the crossing of single-ended signals).
Where x is any one of the parallel channels and y is any other channel.
4
BB [ BURR-BROWN CORPORATION ]
