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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
ELECTRICAL CHARACTERISTICS
T
= −40°C, and T
= +85°C. Typical values are at T = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
MIN
MAX A
LVDD = 3.3V, −0.5dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5273
MIN
TYP
MAX
PARAMETER
TEST CONDITIONS
UNITS
DC ACCURACY
No Missing Codes
DNL Differential Nonlinearity
INL Integral Nonlinearity
Assured
TBD
TBD
TBD
0.5
1
TBD
TBD
TBD
LSB
LSB
(1)
Midscale Offset Error
mV
Offset Temperature Coefficient
(2)
Fixed Gain Error
TBD
1.0
ppm/°C
%FS
∆%/°C
TBD
TBD
Gain Temperature Coefficient
POWER SUPPLY
Total Supply Current
TBD
I
V
V
= FS, F = 10MHz
IN
= FS, F = 10MHz
IN
333
289
mA
mA
CC
IN
IN
IN
I(AVDD) Analog Supply Current
V
= FS, F = 10MHz,
IN
I(LVDD) Digital Output Driver Supply Current
44
mA
W
LVDS Into 100Ω Load
Power Dissipation
V
IN
= FS, F = 10MHz
1.1
IN
REFERENCE VOLTAGES
VREF
Reference Top (internal)
Reference Bottom (internal)
Common-Mode Voltage
2.0
1.0
V
V
T
N
VREF
V
CM
1.5
V
V
Output Current
TBD
mA
V
CM
VREF
Reference Top (external)
1.875
T
B
VREF
Reference Bottom (external)
(3)
Reference Input Resistance
1.125
V
TBD
ANALOG INPUT
DC Differential Input Resistance
1.2
7
kΩ
pF
V
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
V
CM
0.05
2.0
1.5
V
PP
Differential Input Signal at 4V
PP
CLK
Cycles
Voltage Overload Recovery Time
Input Bandwidth
4
Recovery to Within 1% of Code
−3dBFS
300
MHz
DIGITAL DATA OUTPUTS
Data Bit Rate
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
420
840
MBPS
20
0.6
MHz
V
V
LOW Input Low Voltage
HIGH Input High Voltage
Input Current
0
IN
V
IN
2.1
VDD
V
TBD
5
µA
pF
Input Pin Capacitance
(1)
(2)
Offset Error is the measured deviation of the midscale transition from the ideal midscale transition.
Gain Error is the difference between the nominal and actual offset point on the transfer function after the offset error has been corrected to zero.
The gain point is the mid-step value when the digital output is full-scale.
(3)
Average switching current drawn from external reference. DC component of current is internally generated even in external reference mode.
3