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SBAS305A − JANUARY 2004 − REVISED FEBRUARY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(1)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Voltage Between AVSS and LVSS . . . . . . . . . . . . . . −0.3V to 0.3V
Voltage Between AVDD and LVDD . . . . . . . . . . . . . . −0.3V to 0.3V
Voltages Applied to External REF Pins . . . . . . . . . . −0.3V to 2.4V
All LVDS Data and Clock Outputs . . . . . . . . . . . . . . −0.3V to 2.4V
ADCLK Peak Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD
Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . −30mA
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Operating Free-Air Temperature Range, T . . . . . . −40°C to 85°C
A
Lead Temperature 1.6mm (1/16″ from case for 10s) . . . . . . 235°C
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
(1)
ADS5273
HTQFP-80
PFP
−40°C to +85°C
ADS5273IPFP
ADS5273IPFP
ADS5273IPFPT
Tray, 96
″
″
″
″
″
Tape and Reel, 250
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
ADS5273
TYP
MIN
MAX
UNIT
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL), 1/t
Low Voltage Level Clock
20
70
1
MSPS
V
C
High Voltage Level Clock
2
V
ADCLK and ADCLK Outputs (LVDS)
35
70
420
+85
MHz
MHz
°C
P
N
(1)
LCLK and LCLK Outputs (LVDS)
210
−40
P
N
Operating Free-Air Temperature, T
A
(1)
6 × ADCLK.
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
2.0V
Internal Reference
Default with internal pull-up.
1
0
PP
Internal reference is powered down. Common mode of external reference should be within
50mV of V . V is derived from the internal bandgap voltage.
External Reference
CM CM
2
BB [ BURR-BROWN CORPORATION ]
