this case the power dissipation is typically 15mW. With 10µF
external decoupling capacitor at REFT and REFB, it takes
about 800µs to fully restore normal operation after the normal
mode is enabled. Setting QPD to logic high (and STPD to
logic low) will shut down the internal ADC core while the
internal reference circuit power remains on. In this case,
power dissipation is typically 75mW. It takes about 2µs to
fully restore normal operation after the normal mode is
enabled. During power-down, data in the converter pipeline
will be lost and new valid data will be subject to the specified
pipeline delay.
should be bypassed with a combination of 0.1µF ceramic
chip capacitors (0805, low ESR) and a 10µF tantalum tank
capacitor. A similar approach may be used on the digital
supply pins DVDD and driver supply pins, VDRV. In order to
minimize the lead and trace inductance, the capacitors must
be located as close to the supply pins as possible. They are
best placed directly under the package where double-sided
component mounting is allowed. In addition, larger bipolar
decoupling capacitors (2.2µF to 10µF), effective at lower
frequencies, may also be used on the main supply pins. They
can be placed on the PC board in close proximity
(< 0.5 inches) to the ADC. If the analog inputs to the
ADS5220 are driven differentially, it is especially important to
optimize towards a highly symmetrical layout. Small trace
length differences can create phase shifts compromising a
good distortion performance. For this reason, the use of two
single op amps rather than one dual amplifier enables a more
symmetrical layout and a better match of parasitic capaci-
tances. The pin orientation of the ADS5220 package follows
a flow-through design with the analog inputs located on one
side of the package, whereas the digital outputs are located
on the opposite side of the quad-flat package. This provides
a good physical isolation between the analog and digital
connections. While designing the layout, it is important to
keep the analog signal traces separated from any digital lines
to prevent noise coupling onto the analog portion. Try to
match trace length for the differential clock signal (if used) to
avoid mismatches in propagation delays. Single-ended clock
lines must be short and should not cross any other signal
traces. Short circuit traces on the digital outputs will minimize
capacitive loading. Trace length must be kept short to the
receiving gate (< 2 inches) with only one CMOS gate con-
nected to one digital output. If possible, the digital data
outputs should be buffered (with the TI SN74LTH16374, for
example). Dynamic performance can also be improved with
the insertion of series resistors at each data output line. This
sets a defined time constant and reduces the slew rate that
would otherwise flow as the fast edge rate. The resistor value
may be chosen to give a time constant of 15% to 25% of the
used data.
LAYOUT AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high-
frequency designs. Achieving optimum performance with a
fast sampling converter like the ADS5220 requires careful
attention to the PC board layout in order to minimize the
effect of board parasitics and optimize component place-
ment. A multi-layer board usually ensures best results and
allows convenient component placement. The ADS5220 must
be treated as an analog component, and the AVDD pins
connected to a clean analog supply. This ensures the most
consistent results, because digital supplies often carry a high
level of switching noise that could couple into the converter
and degrade the performance. The driver supply pins (VDRV)
must also be connected to a low-noise supply. Supplies of
adjacent digital circuits can carry substantial current tran-
sients. The supply voltage must be thoroughly filtered before
connecting to the VDRV supply of the converter. All ground
connections on the ADS5220 are internally bonded to the
metal flag (bottom of package) that forms a large ground
plane. All ground pins must directly connect to an analog
ground plane that covers the PC board area under the
converter. Due to its high sampling frequency, the ADS5220
generates high frequency current transients and noise (clock
feedthrough) that are fed back into the supply and reference
lines. If not sufficiently bypassed, this adds noise to the
conversion process. See Figure 11 for the recommended
supply decoupling scheme for the ADS5220. All AVDD pins
ADS5220
SBAS261A
17
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