data, when the input voltage changes from normal value to
over FS or from over FS to normal value. The OVR signal
remains high for as long as the input signal exceeds the input
range limits of the ADS5220. The OVR pin is tri-stated by the
use of the output enable pin (OE).
OUTPUT ENABLE (OE
)
The digital outputs including the OVR pin of the ADS5220
can be set to output enable or output high impedance (tri-
state) by the OE pin. For normal operation, this pin must be
at a logic low (default is internal pull-down), whereas a logic
high disables the outputs or sets the output tri-state.
TIMING
The ADS5220 samples the analog signal at the rising edge
of its input clock, and outputs the digital data at the rising
edge of the input clock after a pipeline delay of 5 clocks.
There is an aperture delay (typically 3ns) between the
sampling edge and the actual sampling time. There is also a
propagation delay between the rising edge of the clock and
the time that data is valid on the data bus (see the timing
diagram on page 5). The output data of the ADS5220 is
latched data.
OUTPUT LOADING
It is recommended to keep the capacitive loading on the data
output lines as low as possible, preferably below 10pF.
Higher capacitive loading will cause larger dynamic currents
as the digital outputs are changing. These high current
surges can feed back to the analog portion of the ADC and
adversely affect device performance. If necessary, external
buffers or latches (for example, the SN74LVTH16374) close
to the converter output pins can be used to minimize capaci-
tive loading. Buffers or latches also provide the added benefit
of isolating the ADS5220 from any digital activities on the bus
to limit the high-frequency noise.
POWER SUPPLIES AND
POWER DISSIPATION
OVER-RANGE INDICATOR
ANALOG AND DIGITAL POWER SUPPLY
The ADS5220 has control functions for the input voltage over
full-scale that includes output data code control and over-
range indication. The output data code control of over full-
scale is shown in Table II. In SOB format, for example, when
the input voltage is (+FS – 1 LSB) or above this value, the
ADS5220 outputs all 1s at 12 data bits; when the input
voltage is –FS or below this value, the ADS5220 outputs all
0s at 12 data bits. When the input voltage is 0 (mid-scale) or
only the common-mode voltage at the input, the ADS5220
outputs 1 at MSB and 0s at the remaining 11 data bits.
Another over-range control function of the ADS5220 is over-
range indication, which is output by the OVR pin. The OVR
pin is the function of the reference voltage and the output
data bits, and has the same pipeline delay as the output data
bits. OVR is at logic low if the input voltage is within the FSR,
and is at logic high if the input voltage is over full-scale or
under full-scale. OVR changes from logic low to high or logic
high to low immediately following the change of the output
The ADS5220 includes power-supply pins of AVDD, DVDD
and VDRV. The analog supply AVDD and digital supply DVDD
is +3.3V. The digital output driver supply, VDRV, can be set
between +2.5V and +3.3V. AVDD, DVDD and VDRV are not
tied together internally. Each of these supply pins must be
bypassed separately with at least one 0.1µF ceramic chip
capacitor. The analog supply (AVDD) and the digital supply
(DVDD or VDRV) may be tied together externally with a ferrite
bead or inductor between the supply pins. The ADS5220 is
specified with the digital output driver supply, VDRV, set to
+2.5V. It is highly recommended to consider linear supplies
instead of switching types. Even with good filtering, switching
supplies can radiate noise that could interfere with any high-
frequency input signal and cause unwanted modulation prod-
ucts. The supply voltage should stay within the tolerance
given in the specification table. A basic application configu-
ration with the power supply decoupling is shown in Figure
11.
ADS5220
SBAS261A
15
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