3.3V
3.3V
10µF
+
10µF
+
0.10µF
0.10µF
2.2µF
+
0.10µF
30
31
42
26
25
24
23
22
10
11
12
13
14
15
16
17
18
19
20
VREF
RSEL
IN
NC
NC
24.9Ω
24.9Ω
1.5VDC
1.5VDC
OVR
22pF
NC
41
35
LATCH
IN
NC
NC
D11 (MSB)
D10
D9
15µF
2.2µF
402Ω
402Ω
2Ω
2Ω
+
34
REFT
NC
+3.3V
(AVDD
)
33
32
10µF
D8
REFB
D7
+
ADS5220
15µF
2.2µF
38
39
40
43
44
D6
AGND
AGND
AGND
DGND
DGND
DGND
D5
D4
D3
D2
45
27
28
29
D1
21
D0 (LSB)
AGND
AGND
AGND
SN74LVTH16374
46
CLK
+
VPULSE
49.9Ω
0.10µF
–
10µF
+
VDRV
NC = No Connection.
FIGURE 11. General Configuration for the ADS5220.
POWER DISSIPATION
POWER DOWN
In normal operating mode (STPD = low and QPD = low), the
typical total power dissipation of the ADS5220 is 195mW.
The majority of the power consumption is due to biasing;
therefore, this part of the total power dissipation is indepen-
dent of the applied clock frequency. The current on the
VDRV supply is directly related to the capacitive loading of
the data output pins; care must be taken to minimize such
loading.
The ADS5220 provides two power-down modes for different
application requirements. One is the Standard Power-Down
(STPD); the second is the Quasi-Power-Down (QPD). Both
pins will assume a logic low level (internal pull-down) and
configure the ADS5220 for normal operation. Setting STPD
to logic high (and QPD to logic low or high) will shut down the
internal ADC core and power down the reference circuit. In
ADS5220
16
SBAS261A
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