Due to the THS4503 driving a capacitive load, small series
resistors in the output ensure stable operation. Further de-
tails of this and other functions of the THS4503 may be found
in its product datasheet, located on the Texas Instruments
web site (www.ti.com). In general, differential amplifiers pro-
vide a high-performance driver solution for applications that
require DC signal coupling.
3.3V
0V
CMOS/TTL
CLK
ADS5220
Clock Source
50Ω
50Ω
Mode Select
As shown in Figure 5, an AC-coupled, single-ended input
configuration is realized with TI’s OPA695 for wideband
applications. For narrowband applications, the OPA2822 can
be used. In Figure 5, the OPA695 is configured for a single
supply +5V and noninverting operation. The AC gain of the
amplifier is 2 and the DC bias of the amplifier is +2.5V, set
by the voltage divider from the op amp power supply. The
OPA695 is a very high bandwidth, current-feedback op amp
that combines 4200V/µs slew rate and low input voltage
noise. The OPA695’s high slew-rate and output drive capa-
bility can support the maximum full-scale input range of the
ADS5220 up to high input frequencies.
DVDD
A = DCA enabled
B = DCA disabled
A
B
FIGURE 6. General Input Clock Interface of ADS5220.
The clock input of the ADS5220 is referenced to the digital
supply (DVDD) and the applied logic levels should comply
with the specified levels (LV-logic). To obtain the specified
level of performance the clock signal applied to the ADS5220
should have as close of a 50% duty cycle as possible. This is
particularly important when the ADS5220 is operated at its
maximum sampling rate. Since this condition cannot always
easily be met, the ADS5220 features an on-chip duty-cycle
adjust (DCA) circuit that allows for additional design flexibil-
ity. The function of this duty cycle adjust circuit is controlled
through the Mode Select pin. Its default configuration is for a
logic low (internal pull-down) which has the DCA circuit
disabled. Applying a logic high, the DCA circuit becomes
activated. Now the incoming clock duty cycle can be in the
range of 35% to 65% and the DCA circuit will adjust this to be
50% for the internal timing. There may be situations where
Further details of the OPA695 can be found in the OPA695
data sheet. The common-mode voltage at the ADS5220
input is +1.25V, set by a voltage divider from +3.3V power
supply. The +3.3V power supply must be decoupled, as
shown in Figure 11.
CLOCK INPUT
The clock input of the ADS5220 is designed to operate with
a single-ended pulse clock with CMOS/TTL level and DC-
coupling. There is no external common-mode voltage re-
quirement at the clock input pin (see Figure 6).
+5V
0.1µF
6.8µF
+5V
1.6kΩ
1kΩ
806Ω
3.3V
0.1µF
0.1µF
30Ω
50Ω
Source
806Ω
487Ω
IN
IN
OPA695
57.6Ω
47pF
47pF
ADS5220
0.1µF
487Ω
0.1µF
1.6kΩ
1kΩ
1.25V
3.3V
FIGURE 5. Single-Ended Input of ADS5220 Driven by OPA695 with Gain = 2.
ADS5220
12
SBAS261A
www.ti.com
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