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ADS1255IDB 参数 Datasheet PDF下载

ADS1255IDB图片预览
型号: ADS1255IDB
PDF下载: 下载PDF文件 查看货源
内容描述: 极低噪声, 24位模拟数字转换器 [Very Low Noise, 24-Bit Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 39 页 / 422 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ꢐꢕ ꢙꢚ ꢋ ꢛ ꢛ  
ꢐꢕ ꢙꢚ ꢋ ꢛ ꢜ  
www.ti.com  
SBAS288D − JUNE 2003 − REVISED AUGUST 2004  
COMMAND DEFINITIONS  
The commands summarized in Table 24 control the operation of the ADS1255/6. All of the commands are stand-alone  
except for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional  
command and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUS  
register sets the order of the bits within the output data. CS must stay low during the entire command sequence.  
Table 24. Command Definitions  
COMMAND  
WAKEUP  
RDATA  
DESCRIPTION  
Completes SYNC and Exits Standby Mode  
Read Data  
1ST COMMAND BYTE  
2ND COMMAND BYTE  
0000 0000  
0000 0001  
0000 0011  
0000 1111  
0001 rrrr  
(00h)  
(01h)  
(03h)  
(0Fh)  
(1xh)  
(5xh)  
(F0h)  
(F1h)  
(F2h)  
(F3h)  
(F4h)  
(FCh)  
(FDh)  
(FEh)  
(FFh)  
RDATAC  
SDATAC  
RREG  
Read Data Continuously  
Stop Read Data Continuously  
Read from REG rrr  
0000 nnnn  
0000 nnnn  
WREG  
Write to REG rrr  
0101 rrrr  
SELFCAL  
SELFOCAL  
SELFGCAL  
SYSOCAL  
SYSGCAL  
SYNC  
Offset and Gain Self-Calibration  
Offset Self-Calibration  
1111 0000  
1111 0001  
1111 0010  
1111 0011  
1111 0100  
1111 1100  
1111 1101  
1111 1110  
1111 1111  
Gain Self-Calibration  
System Offset Calibration  
System Gain Calibration  
Synchronize the A/D Conversion  
Begin Standby Mode  
STANDBY  
RESET  
Reset to Power-Up Values  
Completes SYNC and Exits Standby Mode  
WAKEUP  
NOTE: n = number of registers to be read/written − 1. For example, to read/write three registers, set nnnn = 2 (0010).  
r = starting register address for read/write commands.  
RDATA: Read Data  
Description: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits have been shifted  
out on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new  
data is being updated. See the Timing Characteristics for the required delay between the end of the RDATA command and  
the beginning of shifting data on DOUT: t6.  
DRDY  
DIN  
0000 0001  
DOUT  
SCLK  
MSB  
MidByte  
LSB  
t6  
• • •  
• • •  
Figure 29. RDATA Command Sequence  
34  
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