SYMBOL
DESCRIPTION
MIN
NOM
MAX
UNITS
fXIN
tXIN
t2
XIN Clock Frequency
XIN Clock Period
0.5
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
2000
XIN Clock High
0.4 • tXIN
0.4 • tXIN
t3
XIN Clock LOW
t4
Internal Serial Clock HIGH
tXIN
tXIN
t5
Internal Serial Clock LOW
t6
Data In Valid to Internal SCLK Falling Edge (Setup)
Internal SCLK Falling Edge to Data In Not Valid (Hold)
Data Out Valid to Internal SCLK Falling Edge (Setup)
Internal SCLK Falling Edge to Data Out Not Valid (Hold)
External Serial Clock HIGH
40
20
t7
t8
tXIN –25
tXIN
t9
t10
t11
t12
t13
t14
t15
t16
2.5 • tXIN
2.5 • tXIN
40
External Serial Clock LOW
Data In Valid to External SCLK Falling Edge (Setup)
External SCLK Falling Edge to Data In Not Valid (Hold)
Data Out Valid to External SCLK Falling Edge (Setup)
External SCLK Falling Edge to Data Out Not Valid (Hold)
20
tXIN –40
1.5 • tXIN
Falling Edge of DRDY to First SCLK Rising Edge
(Master Mode, CS Tied LOW)
6 • tXIN
5 • tXIN
3 • tXIN
t17
t18
t19
t20
t21
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data (Master Mode)
ns
ns
Falling Edge of Last SCLK for Register Data to Rising Edge
of DRDY (Master Mode)
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data (Slave Mode)
5.5 • tXIN
4 • tXIN
ns
ns
Falling Edge of Last SCLK for Register Data to Rising Edge
of DRDY (Slave Mode)
5 • tXIN
ns
Falling Edge of DRDY to Falling Edge of CS (Master and
Slave Mode)
0.5 • tXIN
ns
t22
t23
Falling Edge of CS to Rising Edge of SCLK (Master Mode)
5 • tXIN
6 • tXIN
ns
ns
Rising Edge of DRDY to Rising Edge of CS (Master and
Slave Mode)
10
t24
t25
Falling Edge of CS to Rising Edge of SCLK (Slave Mode)
5.5 • tXIN
3 • tXIN
2 • tXIN
ns
ns
Falling Edge of Last SCLK for INSR to SDIO Tri-state
(Master Mode)
2 • tXIN
2 • tXIN
t26
t27
SDIO as Output to Rising Edge of First SCLK for Register
Data (Master and Slave Modes)
ns
ns
Falling Edge of Last SCLK for INSR to SDIO Tri-state
(Slave Mode)
4 • tXIN
t28
t29
SDIO Tri-state Time (Master and Slave Modes)
tXIN
tXIN
ns
ns
Falling Edge of Last SCLK for Register Data to SDIO Tri-State
(Master Mode)
t30
Falling Edge of Last SCLK for Register Data to SDIO
Tri-state (Slave Mode)
3 • tXIN
ns
t31
t32
t33
t34
DRDY Fall Time
DRDY Rise Time
30
30
ns
ns
ns
ns
Minimum DSYNC LOW Time
10.5 • tXIN
DSYNC Valid HIGH to Falling Edge of XIN (for Exact
Synchronization of Multiple Converters only)
10
t35
t36
t37
t38
Falling Edge of XIN to DSYNC Not Valid LOW (for Exact
Synchronization of Multiple Converters only)
10
ns
ns
ns
ns
Falling Edge of Last SCLK for Register Data to Rising Edge
of First SCLK of next INSR (Slave Mode, CS Tied LOW)
20.5 • tXIN
10.5 • tXIN
5.5 • tXIN
Rising Edge of CS to Falling Edge of CS (Slave Mode,
Using CS)
Falling Edge of DRDY to First SCLK
Rising Edge (Slave Mode, CS Tied LOW)
TABLE XV. Digital Timing Characteristics.
ADS1210, ADS1211
23
SBAS034B
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