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ADS1210U/1K 参数 Datasheet PDF下载

ADS1210U/1K图片预览
型号: ADS1210U/1K
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, Delta-Sigma, 24-Bit, 1 Func, 4 Channel, Serial Access, PDSO18, GREEN, PLASTIC, SOP-18]
分类和应用: 光电二极管转换器
文件页数/大小: 50 页 / 1178 K
品牌: BB [ BURR-BROWN CORPORATION ]
 浏览型号ADS1210U/1K的Datasheet PDF文件第23页浏览型号ADS1210U/1K的Datasheet PDF文件第24页浏览型号ADS1210U/1K的Datasheet PDF文件第25页浏览型号ADS1210U/1K的Datasheet PDF文件第26页浏览型号ADS1210U/1K的Datasheet PDF文件第28页浏览型号ADS1210U/1K的Datasheet PDF文件第29页浏览型号ADS1210U/1K的Datasheet PDF文件第30页浏览型号ADS1210U/1K的Datasheet PDF文件第31页  
For example, Figure 24 shows that just prior to the DRDY  
signal going LOW, the internal Data Output Register (DOR)  
is updated. This update involves the Offset Calibration  
Register (OCR) and the Full-Scale Register (FSR). If the  
OCR or FSR are being written, their final value may not be  
correct, and the result placed into the DOR will certainly not  
be valid. Problems can also arise if certain bits of the  
Command Register are being changed.  
initiated, the update is blocked. The old output data will  
remain in the DOR and the new data will be lost. The old  
data will remain valid until the read operation has com-  
pleted. In general, multiple instructions may be issued, but  
the last one in any conversion period should be complete  
within 12 • XIN clock periods of the next DRDY LOW  
time. In this usage, “complete” refers to the point where  
DRDY rises in Figures 17 and 19 (in the Timing Section).  
Consult Figures 25 and 26 for the flow of serial data  
during any one conversion period.  
Note that reading the Data Output Register is an excep-  
tion. If the DOR is being read when the internal update is  
Start  
Reading  
ADS1210/11  
drives DRDY LOW  
Start  
Writing  
ADS1210/11  
drives DRDY LOW  
CS  
CS  
state  
state  
HIGH  
HIGH  
LOW  
LOW  
CS  
Continuous  
Read  
Mode?  
state  
HIGH  
Yes  
LOW  
No  
ADS1210/11  
generates 8 serial clock  
cycles and receives  
Instruction Register  
data via SDIO  
ADS1210/11  
generates 8  
serial clock cycles  
and receives  
Instruction Register  
data via SDIO  
ADS1210/11  
generates n  
serial clock cycles  
and receives  
specified  
Use  
SDIO for  
output?  
Yes  
register data  
via SDIO  
No  
SDIO input to  
output transition  
SDOUT becomes  
active from tri-state  
ADS1210/11  
drives DRDY HIGH  
ADS1210/11 generates n  
serial clock cycles  
ADS1210/11 generates n  
serial clock cycles  
End  
and transmits specified  
register data via SDIO  
and transmits specified  
register data via SDOUT  
SDOUT returns to  
tri-state condition  
SDIO transitions to  
tri-state condition  
ADS1210/11  
drives DRDY HIGH  
End  
FIGURE 25. Flowchart for Writing and Reading Register Data, Master Mode.  
ADS1210, ADS1211  
27  
SBAS034B  
www.ti.com  
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