DATA
DECI-
RATE MATION
(HZ)
RATIO
DR12
DR11
DR10
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1000
500
250
100
60
19
38
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
0
0
77
194
325
390
976
1952
50
20
10
Table XI. Decimation Ratios vs Data Rates (Turbo Mode rate of 1 and 10MHz clock).
The input capacitor sampling frequency and modulator rate
can be calculated from the following equations:
G2-G0 (PGA Control) Bits—The G2-G0 bits control the
gain setting of the PGA, as follows:
fSAMP = G • TMR • fXIN/512
fMOD = TMR • fXIN/512
GAIN
SETTING
AVAILABLE TURBO
MODE RATES
G2
G1
G0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
16
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
Default
where G is the gain setting and TMR is the Turbo Mode
Rate. The sampling frequency of the input capacitor directly
relates to the analog input impedance. The modulator rate
relates to the power consumption of the ADS1210/11 and
the output data rate. See the Turbo Mode, Analog Input, and
Reference Input sections for more details.
1
The gain is partially implemented by increasing the input
capacitor sampling frequency, which is given by the follow-
ing equation:
DR12-DR0 (Decimation Ratio) Bits—The DR12-DR0 bits
control the decimation ratio of the ADS1210/11. In essence,
these bits set the number of modulator results which are used in
the digital filter to compute each individual conversion result.
Since the modulator rate depends on both the ADS1210/11
clock frequency and the Turbo Mode Rate, the actual output
data rate is given by the following equation:
fSAMP = G • TMR • fXIN/512
where G is the gain setting and TMR is the Turbo Mode
Rate. The product of G and TMR cannot exceed 16. The
sampling frequency of the input capacitor directly relates to
the analog input impedance. See the Programmable Gain
Amplifier and Analog Input sections for more details.
fDATA = fXIN • TMR/(512 • (Decimation Ratio + 1))
CH1-CH0 (Channel Selection) Bits—The CH1 and CH0 bits
control the input multiplexer on the ADS1211, as follows:
where TMR is the Turbo Mode Rate. Table XI shows
various data rates and corresponding decimation ratios (with
a 10MHz clock). Valid decimation ratios are from 19 to
8000. Outside of this range, the digital filter will compute
results incorrectly due to inadequate or too much data.
CH1
CH0
ACTIVE INPUT
0
0
1
1
0
1
0
1
Channel 1
Channel 2
Channel 3
Channel 4
Default
Data Output Register (DOR)
The DOR is a 24-bit register which contains the most recent
conversion result (see Table XII). This register is updated
with a new result just prior to DRDY going LOW. If the
contents of the DOR are not read within a period of time
defined by 1/fDATA –12•(1/fXIN), then a new conversion
result will overwrite the old. (DRDY is forced HIGH prior
to the DOR update, unless a read is in progress).
(For the ADS1210, CH1 and CH0 must always be zero.) The
channel change takes effect when the last bit of byte 2 has
been written to the Command Register. Output data will not
be valid for the next three conversions despite the DRDY
signal indicating that data is ready. On the fourth time that
DRDY goes LOW after a channel change has been written
to the Command Register, valid data will be present in the
Data Output Register (see Figure 4).
Most Significant Bit
Byte 2
DOR23
DOR15
DOR7
DOR22 DOR21 DOR20 DOR19 DOR18 DOR17 DOR16
Byte 1
SF2-SF0 (Turbo Mode Rate) Bits—The SF2-SF0 bits
control the input capacitor sampling frequency and modula-
tor rate, as follows:
DOR14 DOR13 DOR12 DOR11 DOR10
Byte 0 Least Significant Bit
DOR4 DOR3 DOR2 DOR1 DOR0
DOR9
DOR8
DOR6
DOR5
TURBO
MODE
RATE
AVAILABLE
PGA
SETTINGS
TABLE XII. Data Output Register.
SF2
SF1
SF0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
16
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
Default
The contents of the DOR can be in Two’s Complement or
Offset Binary format. This is controlled by the DF bit of the
Command Register. In addition, the contents can be limited to
unipolar data only with the U/B bit of the Command Register.
1
ADS1210, ADS1211
21
SBAS034B
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