ADS1208
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SBAS348A–MARCH 2005–REVISED MARCH 2005
Grounding
LAYOUT CONSIDERATIONS
Power Supplies
Analog and digital sections of the system design must
be carefully and cleanly partitioned. Each section
should have its own ground plane, with no overlap
between them. Do not join the ground planes. In-
stead, connect the two planes with a moderate signal
trace underneath the modulator. For multiple modu-
lators, connect the two ground planes as close as
possible to one central location for all of the modu-
lators. In some cases, experimentation may be re-
quired to find the best point to connect the two planes
together.
The ADS1208 has two power supplies, AVDD and
BVDD. If there are separate analog and digital power
supplies on the board, a good design approach is to
have AVDD connected to the analog and BVDD to
the digital power supply. Another possible approach
to control noise is the use of a resistor on the power
supply. The connection can be made between the
ADS1208 power supply pins via a 5Ω resistor. The
combination of this resistor and the decoupling ca-
pacitors between the power supply pins AVDD and
AGND provides some filtering. The analog supply
must be well-regulated and offer low noise. For
designs requiring higher resolution from the
ADS1208, power-supply rejection will be a concern.
The digital power supply has high-frequency noise
that can be coupled into the analog portion of the
ADS1208. This noise can originate from switching
Decoupling
Good decoupling practices must be used for the
ADS1208 and for all components in the system
design. All decoupling capacitors, specifically the
0.1µF ceramic capacitors, must be placed as close as
possible to the respective pin being decoupled. A 1µF
and 10µF capacitor, in parallel with the 0.1µF ceramic
capacitor, can be used to decouple AVDD to AGND.
At least one 0.1µF ceramic capacitor must be used to
decouple BVDD to BGND, as well as for the digital
supply on each digital component
power supplies,
microprocessors,
or DSPs.
High-frequency noise will generally be rejected by the
external digital filter at integer multiples of MCLK.
Just below and above these frequencies, noise will
alias back into the passband of the digital filter,
affecting the conversion result. Inputs to the
ADS1208, such as VIN+, VIN- and MCLK should not be
present before the power supply is turned on. Viol-
ating this condition could cause latch-up. If these
signals are present before the supply is turned on,
series resistors should be used to limit the input
current. Additional user testing may be necessary in
order to determine the appropriate connection be-
tween the ADS1208 and different power supplies.
It is highly recommended to place the 100nF com-
pensation capacitor, which is connected between
AVDD and AGND, directly at pins 3 and 6. Otherwise,
current glitches from the internal circuitry can cause
glitches in the supply, which again causes jitter on the
internal clock signal. This jitter degrades the noise
performance of the ADS1208. The input signals VIN+
and VIN– can be routed underneath this capacitor.
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