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ADS1208IPWG4 参数 Datasheet PDF下载

ADS1208IPWG4图片预览
型号: ADS1208IPWG4
PDF下载: 下载PDF文件 查看货源
内容描述: 2阶Δ-Σ调制器,激励霍尔元件 [2nd-Order Delta-Sigma Modulator with Excitation for Hall Elements]
分类和应用: 转换器光电二极管
文件页数/大小: 22 页 / 369 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS1208  
www.ti.com  
SBAS348AMARCH 2005REVISED MARCH 2005  
modulator. An external reference could vary from  
0.5V to 3V. The modulator input range is defined to  
±VREFIN/20. For a 2.5V reference, the full-scale range  
is ±125mV. The REFIN pin is decoupled from the  
modulator with a buffer.  
also directly proportional to the reference voltage, the  
drift of the reference is actually cancelled out. Be  
aware that this is only the case if the application is  
using IOUT to drive the Hall sensor and if REFIN is  
connected to REFOUT.  
1
RADJ  
YOUT  
X
Current Source for the Hall Element  
Internal circuitry (see Figure 36) forces the IADJ pin  
to a potential of:  
This means that trimming the resistor can calibrate  
the gain of the entire system. The resistor can be  
chosen to be stable over temperature, or to compen-  
sate any temperature behavior of the Hall sensor.  
VREFOUT  
VIADJ + AVDD*  
5
DIGITAL OUTPUT  
+5V  
AVDD  
A differential analog input signal of 0V ideally pro-  
duces a stream of 1s and 0s that are high 50% of the  
time and low 50% of the time. A differential analog  
input of +100mV produces a stream of 1s and 0s that  
are high 80% of the time. A differential analog input  
of –100mV produces a stream of 1s and 0s that are  
high 20% of the time. The input voltage versus the  
output modulator signal is shown in Figure 37.  
VREF/5  
RADJ  
e.g., 100  
for 5mA  
VADJ = 0.5V  
IADJ  
RI = 0.3  
IOUT  
ROUT  
DIGITAL INTERFACE  
Introduction  
Figure 36. Current Source  
This means that the voltage drop of the resistor RADJ  
The analog signal that is connected to the input of the  
delta-sigma modulator is converted using the clock  
signal that is applied to the modulator. The result of  
the conversion, or modulation, is the output signal  
MDATA from the delta-sigma modulator. In most  
applications, the two standard signals (MCLK and  
MDATA) are provided from the modulator to an ASIC,  
FPGA, DSP, or µC (each with an implemented filter,  
respectively). A single wire interface is provided in  
Mode 2, where the data stream is Manchester  
encoded. This configuration reduces the costs for  
galvanic isolation.  
is equal to the current source reference VADJ  
.
VREFOUT  
VADJ  
+
+ 0.5 V  
5
With resistor RADJ placed between AVDD and IADJ, a  
current of:  
VREFOUT  
IOUT  
+
ǒ
Ǔ
5 @ RADJ)0.3W  
is sourced out of the IOUT pin. The current should be  
set between 1mA and 8mA. However, it is also  
possible to leave the pin open. As the Hall voltage is  
directly proportional to this current, the input voltage  
to the modulator VIN is directly proportional to the  
internal reference voltage VREFOUT. As the filtered  
digital output data word YOUT from the modulator is  
The interface also provides the inverted outputs  
MDATA and MCLK for the signals MDATA and  
MCLK, respectively. These inverted outputs are use-  
ful for systems with high common-mode noise at the  
digital data transmission. The digital interface is  
specified for the voltage range of 2.7V to 5.5V.  
Modulator Output  
+FS (Analog Input)  
FS (Analog Input)  
Analog Input  
Figure 37. Analog Input vs Modulator Output of the ADS1208  
16  
 
 
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