ADS1208
www.ti.com
SBAS348A–MARCH 2005–REVISED MARCH 2005
Mode 2
Different Modes of Operation
In Mode 2, the internal RC oscillator is running. The
data is Manchester encoded and is provided at the
MDATA and MDATA pins. There is no clock output in
this mode. The MCLK and MCLK outputs are set to
low. The Manchester coding allows the data transfer
with only a single wire. See Figure 3 on page 6.
The typical system clock of the ADS1208 is 20MHz.
The system clock can be provided either from the
internal 20MHz RC oscillator or from an external
clock source. For this reason, the MCLK pin is
bidirectional and is controlled by the mode setting.
The system clock is divided by two for the modulator
clock. Therefore, the default clock frequency of the
modulator is 10MHz. With a possible external clock
range of 1MHz to 24MHz, the modulator operates
between 500kHz and 12MHz. The four modes of
operation for the digital data interface are shown in
Table 2.
Mode 3
In Mode 3, the internal RC oscillator is disabled. The
system clock must be provided externally at the input
MCLK. The system clock must have twice the fre-
quency of the chosen modulator clock. The data is
provided at the MDATA and MDATA output pins.
Since the modulator runs with half the frequency of
the system clock, the data changes at every other
falling edge of the external clock. The data can be
safely strobed at every rising edge of the MCLK
output, which provides half the frequency of the
system clock. This mode allows synchronous oper-
ation to any digital system or the use of modulator
clocks different from 10MHz. See Figure 4 on page 6.
Mode 0
In Mode 0, the internal RC oscillator is running. The
data is provided at the MDATA and MDATA output
pins, and the modulator clock at the MCLK and
MCLK pins. The data changes at the falling edge of
MCLK. Therefore, it can safely be strobed with the
rising edge. See Figure 1 on page 5.
Mode 1
Filter Usage
In Mode 1, the internal RC oscillator is running. The
data is provided at the MDATA and MDATA output
pins. The frequency at the MCLK and MCLK pins is
equivalent to the modulator clock frequency divided
by two. The data must be strobed at both the rising
and falling edges of MCLK. The data at MDATA
changes in the middle, between the rising and falling
edge. In this mode, the frequency of both MCLK and
MDATA is only 5MHz. See Figure 2 on page 5.
The modulator generates only a bitstream, which is
different from the digital word of an analog-to-digital
converter (ADC). In order to output a digital word
equivalent to the analog input voltage, the bitstream
must be processed by a digital filter. A very simple
filter built with minimal effort and hardware is the
Sinc3 filter, shown in Equation 1:
3
1*z*OSR
H(z) + ǒ
Ǔ
(1)
Table 2. Operating Mode Definition and Description
MODE DEFINITION
M1
M0
Mode 0
Mode 1
Mode 2
Mode 3
Internal clock, synchronous data output
Low
Low
High
High
Low
High
Low
High
Internal clock, synchronous data output, half output clock frequency
Internal clock, Manchester encoded data output, no clock output
External clock, synchronous data output
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