Mode 2
Mode 3
In mode 2, M0 is low and M1 is HIGH (see Table I). The control
signal coming from the decoder enables the internal RC oscil-
lator that provides the clock signal INTCLK as an input to MUX1.
Another control signal coming from the decoder positions MUX1
so that the output signal that is the input signal to the code
generator is INTCLK. The output signal MDAT comes from the
code generator because the control signal from the decoder
positions MUX3 for that operation. The DATA signal coming
from the delta-sigma modulator enters the code generator,
where it combines with the clock signal, and twinned binary
coding is implemented as split phase or Manchester coding,
providing the output signal for MUX3. The MCLK output clock
is not active, as multiplexers MUX2 and MUX4 are positioned
for this mode controlled by the control signals coming from the
decoder. The signals timings for mode 2 operation are pre-
sented in Figure 8. In this mode, DSP or µC need to derive the
clock signal from the received waveform itself. Different clock
recovery networks can be implemented.
mode 3 is similar to mode 0; the only difference is that an
external clock (EXTCLK) is provided. In mode 3, both input
signals M0 and M1 are HIGH (see Table I). The control
signal coming from the decoder disables the internal RC
oscillator. The input signal EXTCLK provides the clock
signal as an input to MUX1. The control signal coming from
the decoder positions MUX1 so that the output signal that
is the input signal to the code generator is EXTCLK. The
output signal MDAT is the DATA signal coming directly from
the delta-sigma modulator because the control signal from
the decoder positions MUX3 for that operation. The signal
timings for mode 3 operation are presented in Figure 9. In
this mode, DSP or µC read data on every falling edge of the
input clock.
CLK
DATA
MCLK
MDAT
FIGURE 8. Signal Timing in Mode 2.
MCLK
CLK
DATA
MDAT
FIGURE 9. Signal Timing in Mode 3.
ADS1202
15
SBAS275
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