DIGITAL OUTPUT
ods can be used to obtain this synchronization. The first
method has the delta-sigma modulator and the filter receive
the clock signal from the master clock. The second method
has the delta-sigma modulator transmit the clock signal
together with the data signal. The third method has the filter
derivate the clock signal from the received waveform itself.
The timing diagram for the ADS1202 data retrieval is shown
in the Timing Diagrams. When an external clock is applied to
MCLK, it is used as a system clock by the ADS1202, as well
as a framing clock for data out (this procedure, however, can
only be utilized in mode 3). The modulator output data, which
is a serial stream, is available on the MDAT pin. Typically,
MDAT is read on the falling edge of MCLK.
An ideal solution is a delta-sigma modulator with a flexible
interface, such as the ADS1202, which can provide flexible
output format on the output lines MCLK and MDAT, thus
covering different modes of operation. The signal type that
can be provided is selected with control signals M0 and M1.
An input differential signal of 0V will ideally produce a stream
of ones and zeros that are HIGH 50% of the time and LOW
50% of the time. A differential input of 256mV will produce a
stream of ones and zeros that are HIGH 80% of the time. A
differential input of –256mV will produce a stream of ones
and zeros that are HIGH 20% of the time. The input voltage
versus the output modulator signal is shown in Figure 4.
FLEXIBLE DELTA-SIGMA INTERFACE
Figure 5 illustrates the flexible interface of the ADS1202
delta-sigma converter. The control signals M0 and M1 are
entered in the decoder that decodes the input code and
selects the desired mode of operation. Five output signals
from the decoder control the RC oscillator, multiplexer MUX1,
multiplexer MUX2, multiplexer MUX3, and multiplexer MUX4.
DIGITAL INTERFACE
INTRODUCTION
The analog signal that is connected to the input of the delta-sigma
modulator is converted using the clock signal (CLK) applied to the
modulator. The result of the conversion, or modulation, is the
output signal DATA from the delta-sigma modulator.
MUX1 is controlled by the decoder signal. When the internal
RC oscillator is used, the control signal from the decoder
enables the RC oscillator. At the same time, MUX1 uses the
INTCLK signal as a source for the output signal from MUX1,
which is entering the code generator. If the external clock is
used, the control signal from the decoder disables the inter-
nal RC oscillator and the control signal from the decoder, and
positions MUX1 so that EXTCLK provides the output signal
from MUX1 as the input in the code generator.
In most applications where direct connection is realized
between delta-sigma modulator and DSP or uC, two stan-
dard signals are provided. The MDAT and MCLK signals
provide the easiest means of connection. If it is required to
reduce the number of connection lines, having two signals is
sometimes not an optimal solution.
MUX2 selects the output clock, OCLK. The control signal
coming from the decoder controls the output clock. Two
signals come from the code generator as a half clock fre-
quency, CLK/2, and as a quarter clock frequency, CLK/4,
and provide MUX2 with the input signal. The control signal
will select two different output modes on the OCLK signal as
half clock or quarter clock.
The receiver, DSP, or other control circuit must sample the
output data signal from the modulator at the precise sampling
instant. To do this, sampling a clock signal at the receiver is
needed in order to synchronize with the clock signal at the
transmitter. The delta-sigma modulator clock signal, receiver,
filter, and clock must be synchronized. Three general meth-
Modulator Output
+FS (Analog Input)
–FS (Analog Input)
Analog Input
FIGURE 4. Analog Input Versus Modulator Output of the ADS1201.
ADS1202
12
SBAS275
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