Mode 0
Mode 1
In mode 0 both input signals, M0 and M1, are LOW. The
control signal coming from the decoder enables the internal
RC oscillator that provides the clock signal INTCLK as an
input to MUX1. The control signal coming from the decoder
also positions MUX1 so that the output signal, which is an
input signal for the code generator, is INTCLK. Another
control signal from the decoder circuit positions MUX3 so
that the source for the output signal MDAT is the signal
arriving directly from the delta-sigma modulator, DATA. MUX2
is positioned for the mode controlled by the signal coming
from the decoder so output signal OCLK is CLK/2. The signal
timings for mode 0 operation are presented in Figure 6. In
this mode, DSP or µC read MDAT data on every rising edge
of the MCLK output clock.
In mode 1, the input signal M0 is HIGH and M1 is LOW (see
Table I). The first control signal coming from the decoder
enables the internal RC oscillator that provides clock signal
INTCLK as an input to MUX1. The second control signal
coming from the decoder positions MUX1 so that the output
signal that is the input signal to the code generator is
INTCLK. The output signal from the delta-sigma modulator,
DATA, is also the MDAT signal coming from the modulator
because the control signal from the decoder positions MUX3
for that operation. MUX2 is positioned for the mode con-
trolled by the control signal coming from the decoder with an
OCLK of CLK/2. Output clock signal MCLK comes through
MUX4 from MUX2 as OCLK or CLK/2. The signal timings for
mode 1 operation are presented in Figure 7. In this mode,
DSP or µC read data on every edge, rising and falling, of the
output clock.
CLK
DATA
MCLK
MDAT
FIGURE 6. Signal Timing in Mode 0.
CLK
DATA
MCLK
MDAT
FIGURE 7. Signal Timing in Mode 1.
14
ADS1202
SBAS275
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