C4
0.1µF
ADS1202
VDD
R1
27Ω
M0
VIN
+
MCLK
MDAT
GND
+
VIN
–
C1
0.1µF
RSENSE
M1
–
C5
0.1µF
ADS1202
VDD
R2
27Ω
M0
VIN
+
MCLK
MDAT
GND
+
VIN
–
C2
0.1µF
RSENSE
M1
–
C28x
or
C24x
CVDD
C6
0.1µF
ADS1202
VDD
R3
27Ω
M0
VIN
SPICLK
SPISIMO
SPISIMO
SPISIMO
DVDD
+
MCLK
MDAT
GND
+
VIN
–
C3
0.1µF
RSENSE
M1
–
CLK
FIGURE 13. Parallel Operation of ADS1202 in Mode 3.
input current. Experimentation may be the best way to
determine the appropriate connection between the ADS1202
and different power supplies.
LAYOUT CONSIDERATIONS
POWER SUPPLIES
The ADS1202 requires only one power supply (VDD). If there
are separate analog and digital power supplies on the board,
a good design approach is to have the ADS1202 connected
to the analog power supply. Another approach to control the
noise is the use of a resistor on the power supply. The
connection can be made between the ADS1202 power-
supply pins via a 10Ω resistor. The combination of this
resistor and the decoupling capacitors between the power-
supply pins on the ADS1202 provide some filtering. The
analog supply that is used must be well regulated and low
noise. For designs requiring higher resolution from the
ADS1202, power-supply rejection will be a concern. The
digital power supply has high-frequency noise that can be
capacitively coupled into the analog portion of the ADS1202.
This noise can originate from switching power supplies,
microprocessors, or digital signal processors. High-frequency
noise will generally be rejected by the external digital filter at
integer multiples of MCLK. Just below and above these
frequencies, noise will alias back into the passband of the
digital filter, affecting the conversion result. Inputs to the
ADS1202, such as VIN+, VIN–, and MCLK should not be
present before the power supply is on. Violating this condi-
tion could cause latch-up. If these signals are present before
the supply is on, series resistors should be used to limit the
GROUNDING
Analog and digital sections of the design must be carefully
and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. Do not join the
ground planes, but connect the two with a moderate signal
trace underneath the converter. For multiple converters,
connect the two ground planes as close as possible to one
central location for all of the converters. In some cases,
experimentation may be required to find the best point to
connect the two planes together.
DECOUPLING
Good decoupling practices must be used for the ADS1202
and for all components in the design. All decoupling capaci-
tors, specifically the 0.1µF ceramic capacitors, must be
placed as close as possible to the pin being decoupled. A
1µF and 10µF capacitor, in parallel with the 0.1µF ceramic
capacitor, must be used to decouple VDD to GND. At least
one 0.1µF ceramic capacitor must be used to decouple VDD
to GND, as well as for the digital supply on each digital
component.
ADS1202
18
SBAS275
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