THEORY OF OPERATION
GENERAL DESCRIPTION
The differential analog input of the ADS1202 is implemented
with a switched capacitor circuit. This switched capacitor
circuit implements a 2nd-order modulator stage, which digi-
tizes the input signal into a 1-bit output stream. The sample
clock (MCLK) provides the switched capacitor network and
modulator clock signal for the A/D conversion process, as
well as the output data-framing clock. The clock source can
be internal as well as external. Different frequencies for this
clock allow for a variety of solutions and signal bandwidths
(however, this can only be utilized in mode 3). The analog
input signal is continuously sampled by the modulator and
compared to an internal voltage reference. A digital stream,
which accurately represents the analog input voltage over
time, appears at the output of the converter.
The ADS1202 is a single-channel, 2nd-order, CMOS analog
modulator designed for medium to high resolution conver-
sions from DC to 39kHz with an oversampling ratio (OSR) of
256. The output of the converter (MDAT) provides a stream
of digital ones and zeros. The time average of this serial
output is proportional to the analog input voltage. The com-
bination of an ADS1202 and a Digital Signal Processor
(DSP) that is programmed to implement a digital filter results
in a medium resolution A/D converter system. This system
allows flexibility with the digital filter design and is capable of
A/D conversion results that have a dynamic range that
exceeds 85dB with OSR = 256.
+5V
+5V
DSP
VDDO
M
0.1µF
ADS1202
10nF
M0
VDD
27Ω
SPICLK
VIN
VIN
M1
+
MCLK
MDAT
GND
SPISIMO
VSSO
–
27Ω
0.1µF
0.1µF
FIGURE 1. Connection Diagram for the ADS1202 Delta-Sigma Modulator Including DSP.
ADS1202
10
SBAS275
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